• 전자공학회논문지D
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• 제36D권6호
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• pp.71-78
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• 1999

본 논문에서는 마이크로웨이브 대역의 OPLL 해석시 루프 시간 지연뿐만 아니라 기존의 연구에서는 고려하지 않았던 반도체 VCO laser의 주파수 응답을 모델링하여 OPLL의 성능에 미치는 영향을 분석하였다. 루프 시간 지연은 시스템의 안정성과 레이저의 최대 허용 선폭에 대한 조건을 더욱 엄격하게 함을 확인할 수 있었다. 또한 VCO laser의 주파수 응답을 고려할 경우 레이저의 최대 허용 선폭을 최적화된 값으로 설정할 수 있음을 확인할 수 있었다. 따라서, 대역폭이 큰 OPLL을 설계할 경우에는 루프 시간 지연뿐만 아니라 VCO laser의 주파수 응답 특성까지도 고려되어야 한다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2005년도 추계종합학술대회
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• pp.829-832
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• 2005

This paper describes a wide-range dual-loop Delay Locked Loop (DLL) using Voltage Controlled Delay Line (VCDL) based on Transmission Gate(TG) inverters. One loop is used when the minimum VCDL delay is greater than a half of $T_{REF}$, the reference clock period. The other loop is initiated when the minimum delay is less than $0.5{\times}T_{REF}$. The proposed VCDL improves the dynamic operation range of a DLL. The DLL with a VCDL of 10 TG inverters provides a lock range from 70MHz to 700MHz when designed using $0.18{\mu}m$ CMOS technology with 1.8 supply voltage. The DLL consumes 11.5mW for locking operation with a 700MHz reference clock. The proposed DLL can be used for high-speed memory devices and processors, communication systems, high-performance display interfaces, etc.

• Journal of Multimedia Information System
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• 제5권2호
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• pp.139-142
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• 2018

This work presents a novel architecture of phase locked loop (PLL) with the current compensating scheme to improve phase noise characteristic. The proposed PLL has two charge pumps (CP), main-CP (MCP) and sub-CP (SCP). The smaller SCP current with same time duration but opposite direction of UP/DN MCP current is injected to the loop filter (LF). It suppresses the voltage fluctuation of LF. The PLL has a novel voltage controlled oscillator (VCO) consisting of a voltage controlled resistor (VCR) and the three-stage ring oscillator with latch type delay cells. The VCR linearly converts voltage into current, and the latch type delay cell has short active on-time of transistors. As a result, it improves phase noise characteristic. The proposed PLL has been fabricated with $0.35{\mu}m$ 3.3 V CMOS process. Measured phase noise at 1 MHz offset is -103 dBc/Hz resulting in 3 dBc/Hz phase noise improvement compared to the conventional PLL.

• 한국통신학회:학술대회논문집
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• 한국통신학회 1998년도 하계종합학술발표회 논문집(하)
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• pp.1196-1199
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• 1998

• 대한전자공학회논문지SD
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• 제37권7호
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• pp.43-49
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• 2000

본 논문에서는 DDR(Double Data Rate) Synchronous DRAM에서 안전한 데이터 영역(tDV) 확보를 위한 DDL(Delay Locked Loop) 회로인 ADD(Alternate Directional Delay)회로 방식을 제안하였다. 본 방식은 디지털 DLL의 단점인 부가회로 면적(area-overhead)을 절감할 수 있는 방식으로ㅆ, 하나의 지연회로 체인(chain)을 이용하여 동시에 양방향으로 클럭을 발생할 수 있도록 함으로써 기존의 SMD(Synchronous Mirror Delay)방식에 비해 약 2배의 부가회로 면적을 감소할 수 있도록 설계하였다. 또한 설계한 ADD방식이 지터(jitter)는 50ps-140ps이고, 동ㅈ가 주파수 영역은 166MHz-66MHz이다.(205V, TYP, 동작조건)

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.387-394
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• 2016

This paper presents a fully digital delay locked loop (DLL) that can acquire lock in four clock cycles with a resolution of a 1/4 NAND-delay. The proposed DLL with a multi-dither-free phase detector acquires the initial lock in four clock cycles with 1/2 NAND-delay. Then, it utilizes a multi-dither-free phase detector, a region accumulator, and phase blenders, to improve the resolution to a 1/4 NAND-delay. The region accumulator which continuously steers the control registers and the phase blender, adaptively controls the tracking bandwidth depending on the amount of jitter, and effectively suppresses the dithering jitter. Fabricated in a 65 nm CMOS process, the proposed DLL occupies $0.0432mm^2$, and consumes 3.7 mW from a 1.2-V supply at 2 GHz.

• 한국정보통신학회논문지
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• 제21권7호
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• pp.1261-1266
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• 2017

지연 시간 전압 분산 변환기 (DVVC) 및 평균 회로 (AC)가 있는 지터 억제 지연 고정 루프 (DLL) 기반 클록 발생기를 제안하였다. 제안한 클록 발생기는 지연고정루프에서 무작위로 발생하는 지터와 회로의 구조에 의해 발생하는 지터를 억제하도록 하였다. 지연 시간 전압 분산 변환기는 각 지연단의 지연 차이를 감지하고 출력 전압을 생성한다. 평균회로는 두개의 연속되는 지연 시간 전압 분산 변환기의 출력 전압을 평균화 한다. 지연 시간 전압 분산 변환기 및 평균 회로는 연속적인 지연단의 지연 시간을 평균화하고 모든 지연단의 지연 시간을 동일하게 만든다. 또한 루프필터 출력 전압의 변동을 줄이기 위해 부궤환 기능으로 효과적인 작동을 하는 스위치가 있는 커패시터가 도입되었다. One-poly six-metal $0.18{\mu}m$ CMOS 공정으로 제작 된 DLL 기반 클록 발생기의 측정 결과는 13.4 ps rms 지터특성을 보여준다.

• Journal of Electrical Engineering and Technology
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• 제2권2호
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• pp.165-171
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• 2007

This paper proposes a new islanding detection method for inverter-interfaced distributed generators (DG). To detect islanding conditions, this paper calculates the phase angle variation of the system voltage by using the phase-locked loop (PLL) in the inverter controllers. Because almost all inverter systems are equipped with the PLL, the implementation of this method is fairly simple and economical for inverter-interfaced DGs. The detection time can also be shortened by reducing communication delay between the relays and the DGs. The proposed method is based on the fact that islanding conditions result in the frequency and voltage variation of the islanded area. The variation depends on the amount of power mismatch. To improve the accuracy of the detection algorithm, this paper injects small low-frequency reactive power mismatch to the output power of DG.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권4호
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• pp.303-317
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• 2013

Two novel clocking strategies for a high-speed multi-channel serializer-deserializer (SERDES) are proposed in this paper. Both of the clocking strategies are based on groups, which facilitate flexibility and expansibility of the SERDES. One clocking strategy is applicable to moderate parallel I/O cases, such as high density, short distance, consistent media, high temperature variation, which is used for the serializer array. Each group within the strategy consists of a full-rate phase-locked loop (PLL), a full-rate delay-locked loop (DLL), and two fixed phase alignment (FPA) techniques. The other is applicable to more awful I/O cases such as higher speed, longer distance, inconsistent media, serious crosstalk, which is used for the deserializer array. Each group within the strategy is composed of a PLL and two DLLs. Moreover, a half-rate version is chosen to realize the desired function of 1:2 deserializer. Based on the proposed clocking strategies, two representative ICs for each group of SERDES are designed and fabricated in a standard $0.18{\mu}m$ CMOS technology. Measurement results indicate that the two SERDES ICs can work properly accompanied with their corresponding clocking strategies.

• JSTS:Journal of Semiconductor Technology and Science
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• 제8권3호
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• pp.179-192
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• 2008

A multiphase compensation method with mismatch linearization technique, is presented and demonstrated in a $\Sigma-\Delta$ fractional-N frequency synthesizer. An on-chip delay-locked loop (DLL) and a proposed delay line structure are constructed to provide multiphase compensation on $\Sigma-\Delta$ quantizetion noise. In the delay line structure, dynamic element matching (DEM) techniques are employed for mismatch linearization. The proposed $\Sigma-\Delta$ fractional-N frequency synthesizer is fabricated in a $0.18-{\mu}m$ CMOS technology with 2.14-GHz output frequency and 4-Hz resolution. The die size is 0.92 mm$\times$1.15 mm, and it consumes 27.2 mW. In-band phase noise of -82 dBc/Hz at 10 kHz offset and out-of-band phase noise of -103 dBc/Hz at 1 MHz offset are measured with a loop bandwidth of 200 kHz. The settling time is shorter than $25{\mu}s$.