• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.693-695
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• 2016

A random and systematic jitter suppressed DLL is presented. The AC averages the delay time of successive delay stages and equalizes the delay time of all delay stages. Measurement results of the DLL-based clock generator fabricated in a one-poly six-metal $0.18{\mu}m$ CMOS process shows 13.4-ps rms jitter.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.27-30
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• 2004

This paper has been designed the TDMG(Time Delay Multiple Gaussian) pulse generator for UWB systems and analyzed the characteristics of UWB impulse. Composite two equal Gaussian pulses in a difference time lag, and then investigated TDMG pulse and modeled mathematically. Designed the TDMG pulse generator by ADS(Advanced Design System) to embody by using actual element with such mathematical model. As well as, this paper finally proved an excellence of the TDMG pulse generator by performing analysis through simulation.

• Current Optics and Photonics
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• v.2 no.1
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• pp.53-58
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• 2018

A novel X-band high speed frequency sweep signal generator based on a tunable optoelectronic oscillator (OEO) incorporating a frequency-swept laser is presented and the theoretical fundamentals of the design are explained. A prototype of the generator with tuning range from 8.8552 GHz to 10.3992 GHz and a fine step about 8 MHz is achieved. The generated radiofrequency signal with a single sideband (SSB) phase noise lower than -100 dBc/Hz@10KHz is experimentally demonstrated within the whole tunable range, without any narrow RF band-pass filters in the loop. And the tuning speed of the frequency sweep signal generator can reach to over 1 GHz/s benefiting from applying a novel dispersion compensation modular instead of several tens of kilometers of optical fiber delay line in the system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.1 no.2
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• pp.193-197
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• 1997

In this paper, we propose a new PN chip clock generator which employs two synchronous counters to achieve precise phase control of chip clock. In a CDMA code acquisition and tracking system, the PN chip clock is required to operate highly reliable without any glitch even under harsh environment condition such as temperature and voltage fluctu-aliens. The digital implementation of the proposed PN chip clock generator imparts it with much desired reliability. Since the proposed chip clock generator can be easily controlled into one of the states: free running, phase advance, and delay state, it can be applied to data processing as well as code synchronization. We have done FPGA implementation of the proposed logic and have verified its satisfactory operation up to 50 MHz.

• Journal of the Korean Solar Energy Society
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• v.31 no.4
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• pp.80-86
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• 2011

Investigation of the effective soil thermal conductivity(k) is the first step in designing the ground loop heat exchanger(borehole) of a geothermal heat pump system. Another important factor is the borehole thermal resistance($R_b$). Thermal response tests offer a good method to determine the ground thermal properties for the total heat transport in the ground. This is done by supplying a constant heat power into a borehole heat exchanger. There are two methods to supply a constant heat power. One is to employ the electricity provided by Korea Electric Power Corporation(KEPCO). The other is to use electricity generated by a generator. In this study, the power supply regulation was found to reduce when the electricity generated by the generator was used. This is because the generator evaluated with the power supply characteristically reduces the power supply regulation between an overload and a complex using. But it sometimes occurs a power supply regulation in In-situ thermal response test. In this case getting of k,$R_b$ requires delay times and restored normal state. However, the effect of the delay times and restored normal state on the soil thermal conductivity and borehole thermal resistance is very small. Therefore it is possible to use a generally accepted delay times and restored normal state in the analysis. In this work, it is also shown that an acceptable range of ${\Delta}k$, ${\Delta}R_b$ for normal state and regulation state might be approximately 0.01-0.16W/m k, and -0.004-0.007m K/W, respectively. Thus, restored normal state of power supply regulation is valuable to recommend.

• Proceedings of the KIEE Conference
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• 2008.07a
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• pp.998-998
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• 2008

It is difficult to find for analysis solution of the synchronous generator exciter system. Recently, it had good performance UPS converter system using CRA method. The single converter of synchronous generator excitor system under considerations : (i) the overall system shall keep very low AC-voltage tracking error as well as no phase delay over different load condition, and (ii) the digital controller shall be employed at a fixed sampling. It is shown that the synchronous exciter system can be achieved by the proposed controller using Characteristic Ratio Assignment.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.63 no.2
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• pp.81-88
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• 2014

In this paper, an implementation of concurrent backoff delay process on a single chip with IEEE 802.15.4 hardware and 8051 processor core that can be used for analyzing the interference on IEEE 802.15.4 channels due to WiFi traffics is studied. The backoff delay process of IEEE 802.15.4 CSMA-CA algorithm is explained. The characteristics of random number generator, timer, and CCA register included in the single chip are described with their control procedure in order to implement the process. A concurrent backoff delay process to evaluate multiple IEEE 802.15.4 channels is proposed, and a method to service the associated tasks at sequentially ordered backoff delay events occurring on the channels is explained. For the implementation of the concurrent backoff delay process on a single chip IEEE 802.15.4 hardware, the elements for the single channel backoff delay process and their control procedure are used to be extended to multiple channels with little modification. The medium access delay on each channel, which is available after execution of the concurrent backoff delay process, is displayed on the LCD of an IEEE 802.15.4 channel analyzer. The experimental results show that we can easily identify the interference on IEEE 802.15.4 channels caused by WiFi traffics in comparison with the way displaying measured channel powers.

• Journal of Electrical Engineering and Technology
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• v.10 no.4
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• pp.1453-1459
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• 2015

Loss of excitation (LOE) relay is prevalently used to protect synchronous generator. The widely used method for synchronous generator LOE protection is a negative offset mho relay with two zones. The basis of this relay is identical to mho impedance relay. In other words, this relay calculates impedance by measuring voltage and current at the generator terminal. On the other hand, the presence of series compensation, changes measured voltage and current signals during loss of excitation. This paper reveals that the presence of series compensators such as fixed series capacitors (FSCs) and static synchronous series compensator (SSSC) causes a significant delay on the performance of generator LOE relay. It is also shown that the presence of SSSC causes the LOE relay to be under-reached. Different operating modes of the power system, the SSSC and also different percentages of series capacitive compensations have been considered in the modeling. All the detailed simulations are carried out in the MATLAB/Simulink environment using the SimPowerSystems toolbox.

• Transactions of the Korean Society of Pressure Vessels and Piping
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• v.7 no.3
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• pp.1-7
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• 2011

The analysis shows that the vibration is one of the main reasons of turbine failure. Especially, the problems caused by vibration occur right after retrofit of the turbine-generator and restarting the turbine. Through the case study of high vibration caused by after the turbine trip and restart, turbine vibration was identified to be influenced by startup condition. Turbine startup at high casing temperature right after unscheduled turbine trip cause radial expansion in rotor by contraction in axial direction, while casing continues to contract by steam flowing into casing. Consequently, gap between rotor and casing decrease until to metal contact to cause high vibration. Through the case study of high vibration of turbine-generator system after generator retrofit, it was identified that generator replacement could cause high vibration in turbine-generator system if the influence of generator replacement on entire system was not considered properly. To prevent startup delay caused by high vibration, it is important to keep the gaps at the design standard and start the turbine after thermal equilibrium.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.281-284
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• 2001

This paper describes an analog multi-phase delay-locked loop (DLL) to solve the harmonic lock problem using current-starved inverter and shunt-capacitor delay cell. The DLL can be used not only as an internal clock buffer of microprocessors and memory It's but also as a multi-phase clock generator for gigabit serial interfaces. The proposed circuit was simulated in a 0.25${\mu}{\textrm}{m}$ CMOS technology to solve harmonic lock problem and to realize fast lock-on time and low-jitter we verified time interval less than 40 ps as the simulation results.