• Title/Summary/Keyword: Delay Tool

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Lightweighted CTS Preconstruction Techniques for Checking Clock Tree Synthesizable Paths in RTL Design Time (레지스터 전달 수준 설계단계에서 사전 클럭트리합성 가능여부 판단을 위한 경량화된 클럭트리 재구성 방법)

  • Kwon, Nayoung;Park, Daejin
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.26 no.10
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    • pp.1537-1544
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    • 2022
  • When designing chip, it considers design specification, timing problem, and clock synchronization on place & route (P&R) process. P&R process is complicated because of considering various factors. Chip uses clock tree synthesis (CTS) to reduce clock path delay. The purpose of this study is to examine shallow-CTS algorithm for checking clock tree synthesizable. Using open source Parser-Verilog, register transfer level (RTL) synthesizable Verilog file is parsed and it uses Pre-CTS and Post-CTS process that is included shallow-CTS. Based on longest clock path in the Pre-CTS and Post-CTS stages, the standard deviation before and after buffer insertion is compared and analyzed for the accuracy of CTS. In this paper, It is expected that the cost and time problem could be reduced by providing a pre-clock tree synthesis verification method at the RTL level without confirming the CTS result using the time-consuming licensed EDA tool.

Implementation of Sonar Bearing Accuracy Measurement Equipment with Parallax Error and Time Delay Error Correction (관측위치오차와 시간지연오차를 보정하는 소나방위정확도 측정 장비 구현)

  • Kim, Sung-Duk;Kim, Do-Young;Park, Gyu-Tae;Shin, Kee-Cheol
    • Journal of the Institute of Convergence Signal Processing
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    • v.20 no.4
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    • pp.245-251
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    • 2019
  • Sonar bearing accuracy is the correspondence between the target orientation predicted by sonar and actual target orientation, and is obtained from measurements. However, when measuring sonar bearing accuracy, many errors are included in the results because they are made at sea, where complex and diverse environmental factors are applied. In particular, parallax error caused by the difference between the position of the GPS receiver and the sonar sensor, and the time delay error generated between the speed of underwater sound waves and the speed of electromagnetic waves in the air have a great influence on the accuracy. Correcting these parallax errors and time delay errors without an automated tool is a laborious task. Therefore, in this study, we propose a sonar bearing accuracy measurement equipment with parallax error and time delay error correction. The tests were carried out through simulation data and real data. As a result of the test it was confirmed that the parallax error and time delay error were systematically corrected so that 51.7% for simulation data and more than 18.5% for real data. The proposed method is expected to improve the efficiency and accuracy of sonar system detection performance verification in the future.

BCC Based Mobile WIMAX Initial Network Entry with Improved Security (보안성이 강화된 타원곡선 암호 기반의 Mobile WIMAX 초기 진입 구간)

  • Choi, Do-Hyun;Park, Jung-Oh;Jun, Moon-Seog
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.36 no.11B
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    • pp.1305-1314
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    • 2011
  • Initial entry section has vulnerability which exposes plain text parameter in Mobile WIMAX environment which is the 4th generation technology. Each node message need to be encrypted to prevent the third party attack or message leakage. In this paper, we propose Mobile WIMAX initial entry section encryption using Elliptic Curve Cryptosystem. We have compared proposed model with existing model using OPNET simulator tool. He delay rate has increased little bit in initial entry section than before after the comparison, but it has shown more effective in average delay and throughput than encryption applied other existing model.

Impacts of Trapezoidal Fin of 20-nm Double-Gate FinFET on the Electrical Characteristics of Circuits

  • Ryu, Myunghwan;Kim, Youngmin
    • JSTS:Journal of Semiconductor Technology and Science
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    • v.15 no.4
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    • pp.462-470
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    • 2015
  • In this study, we analyze the impacts of the trapezoidal fin shape of a double-gate FinFET on the electrical characteristics of circuits. The trapezoidal nature of a fin body is generated by varying the angle of the sidewall of the FinFET. A technology computer-aided-design (TCAD) simulation shows that the on-state current increases, and the capacitance becomes larger, as the bottom fin width increases. Several circuit performance metrics for both digital and analog circuits, such as the fan-out 4 (FO4) delay, ring oscillator (RO) frequency, and cut-off frequency, are evaluated with mixed-mode simulations using the 3D TCAD tool. The trapezoidal nature of the FinFET results in different effects on the driving current and gate capacitance. As a result, the propagation delay of an inverter decreases as the angle increases because of the higher on-current, and the FO4 speed and RO frequency increase as the angle increases but decrease for wider angles because of the higher impact on the capacitance rather than the driving strength. Finally, the simulation reveals that the trapezoidal angle range from $10^{\circ}$ to $20^{\circ}$ is a good tradeoff between larger on-current and higher capacitance for an optimum trapezoidal FinFET shape.

DEVELOPMENT OF A STEAM GENERATOR TUBE INSPECTION ROBOT WITH A SUPPORTING LEG

  • Shin, Ho-Cheol;Jeong, Kyung-Min;Jung, Seung-Ho;Kim, Seung-Ho
    • Nuclear Engineering and Technology
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    • v.41 no.1
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    • pp.125-134
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    • 2009
  • This paper presents details on a tube inspection robotic system and a positioning method of the robot for a steam generator (SG) in nuclear power plants (NPPs). The robotic system is separated into three parts for easy handling, which reduces the radiation exposure during installation. The system has a supporting leg to increase the rigidity of the robot base. Since there are several thousands of tubes to be inspected inside a SG, it is very important to position the tool of the robot at the right tubes even if the robot base is positioned inaccurately during the installation. In order to obtain absolute accuracy of a position, the robot kinematics was mathematically modeled with the modified DH(Denavit-Hartenberg) model and calibrated on site using tube holes as calibration points. To tune the PID gains of a commercial motor driver systematically, the time delay control (TDC) based gain tuning method was adopted. To verify the performance of the robotic system, experiments on a Framatomes 51B Model type SG mockup were undertaken.

3-Phase RMS Voltage Measurement Method of Virtual Frequence using Instantaneous Power Component Concept (순시전력 합성 개념을 이용한 가상주파수 3상 실효전압 계측기법)

  • Park, Seong-Mi;Yang, Ji-Hoon;Park, Sung-Jun
    • Journal of the Korean Society of Industry Convergence
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    • v.22 no.3
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    • pp.251-257
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    • 2019
  • This paper proposes a new measurement method using virtual power concept to measure the effective value of 3-phase voltage with variable frequency. The conventional effective value measurement method uses a method of integrating data sampled during one or half cycle of the power voltage and averaging it. In this method, since the effective voltage is calculated every cycle, a time delay occurs in the measured effective voltage and it is s a problem to measure the effective value of a device whose frequency varies from time to time, such as a generator. The proposed 3-phase voltage rms measurement method has an advantage that it can measure accurate voltage RMS value regardless of measurement frequency variation. In particular, there is an advantage in that it is possible to measure a 3-phase effective voltage rather than an average value of the effective voltage of each phase in a 3-phase unbalance voltage. In addition, the validity of the proposed method is verified by using the Psim simulation tool and the experimental results are analyzed by applying the proposed measurement algorithm to the actual three phase synchronous generator voltage measurement experiment.

Performance Analysis of 403.5MHz CMOS Ring Oscillator Implemented for Biomedical Implantable Device (생체 이식형 장치를 위해 구현된 403.5MHz CMOS 링 발진기의 성능 분석)

  • Ferdousi Arifa;Choi Goangseog
    • Journal of Korea Society of Digital Industry and Information Management
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    • v.19 no.2
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    • pp.11-25
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    • 2023
  • With the increasing advancement of VLSI technology, health care system is also developing to serve the humanity with better care. Therefore, biomedical implantable devices are one of the amazing important invention of scientist to collect data from the body cell for the diagnosis of diseases without any pain. This Biomedical implantable transceiver circuit has several important issues. Oscillator is one of them. For the design flexibility and complete transistor-based architecture ring oscillator is favorite to the oscillator circuit designer. This paper represents the design and analysis of the a 9-stage CMOS ring oscillator using cadence virtuoso tool in 180nm technology. It is also designed to generate the carrier signal of 403.5MHz frequency. Ring oscillator comprises of odd number of stages with a feedback circuit forming a closed loop. This circuit was designed with 9-stages of delay inverter and simulated for various parameters such as delay, phase noise or jitter and power consumption. The average power consumption for this oscillator is 9.32㎼ and average phase noise is only -86 dBc/Hz with the source voltage of 0.8827V.

Implementation of a Network Design and Analysis Tool Supporting VoIP Simulations (VoIP 시뮬레이션을 지원하는 네트워크 설계 및 분석 도구의 구현)

  • Choi Jae-Won;Lee Kwang-Hui
    • Journal of the Institute of Electronics Engineers of Korea TC
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    • v.42 no.1
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    • pp.81-89
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    • 2005
  • In this paper, we have described the implementation of a practical simulation tool to design and analyze communication networks. Especially, this study is focused on the implementation and application methods of a simulator supporting VoIP The key characteristics of this particular system are its easy and intuitive usage, the real behaviors implementation of equipment and protocols, the actual generation and transmission of traffic for simulation, supporting of VoIP and so forth. Our system is distinguished from the existing tools which define only the nature of voice traffic, process those packets in the same way as general data, and analyze only the quality of packet transmission such as delay. Our tool presented in this paper generates and processes packets in different way according to the types of traffic distinguishing call signal from voice information traffic. Also, we equipped this system with the various devices such as VoIP gateway and gatekeeper, which enabled this system to analyze the performance of devices and the quality of voice traffic transmission between PSTN and Internet. By presenting the implementation methods and application of this system, we managed to propose the utilization scheme of a simulation tool.

A Study on the Optimization of Grinding Energy Density for a Non-linear Grinding System with Dual Time Delay (이중 시간지연을 가지는 비선형 연삭기의 가공 에너지 밀도 최적화 연구)

  • Jung, Jeehyun;Kim, Pilkee;Lee, Jung-In;Lee, Sooyoung;Lee, Jong-Hang;Kim, Kyung-Dong;Seok, Jongwon
    • Journal of the Korean Society for Precision Engineering
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    • v.30 no.5
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    • pp.493-498
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    • 2013
  • The present study treats the optimization process for a non-linear grinding system with dual time delay, mainly from the energetic viewpoint. To this end, the stability of the grinding system is investigated first with regard to the grinding wheel rotation speed. The concept of grinding energy density is newly proposed as the primary figure of merit and this quantity is evaluated at various stable and limit cycle conditions. The computational results show that simple monotonic trend in energy density is observed under stable conditions, whilst rather complicated behaviors can appear when the conditions are associated with limit cycle oscillations. Finally, the relations between the vibration amplitude and the energy density and their implications on the engineering decision/compromise are discussed.

Analyzing the Changes in Speed Due to High Occupancy Vehicles Using Median Bus Lane (다인승차량의 중앙버스전용차로 이용에 따른 영향분석)

  • Lee, Jung-Beom
    • The Journal of The Korea Institute of Intelligent Transport Systems
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    • v.12 no.4
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    • pp.87-94
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    • 2013
  • This study estimated the changes in delays and speeds of vehicles in exclusive bus lane and road when the High Occupancy Vehicles(HOV) use the median bus lane. Synchro simulation tool was used to optimize the traffic signal time on the network and VISSIM was applied to simulate various scenarios. Here, drivers behavior parameters in VISSIM was optimized using Simultaneous Perturbation Stochastic Approximation(SPSA) algorithm in order to represent real traffic condition. Based on the simulation results, the delay in Doan daero was decreased when the volume of HOV in current condition runs on the median bus lane, whereas delay in Doan dongro was increased in all scenarios. The changes in bus speed was not sharply decreased for both study sites, even though the number of HOV increased to 10%. Thus, it could be allowed that the HOV use the median bus lane in Doan dongro and Doan daero. Future research tasks include studying about changes in delay when the HOV use the curb bus lane.