• 한국도로학회논문집
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• 제8권2호
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• pp.75-85
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• 2006

현재 우리나라 2차로도로 횡단면 설계기준은 설계속도별 최소 차로폭과 길어깨 기준은 있으나, 다양한 횡단면 구성안이 없어 전국이 획일적인 도로구조 형태를 보이고 있다. 따라서 본 연구에서는 2차로도로의 사고유형별 원인을 규명하고 그에 따른 교통운영 및 안전성 측면에서 횡단면 개선 방안을 수립하고, 평가척도를 선정하였으며, 평가과정을 통해 새로운 횡단면 설계기준을 제시하고 이를 검증하였다. 연구결과 같은 2차로도 도로폭 $9{\sim}12.9m$ 보다 $6{\sim}8.9m$ 도로가 사고율이 매우 높은 것으로 나타났으며, 대표적 사고유형들의 개선점은 차로 및 길어깨 확장으로 나타났다. 시뮬레이션 결과 도로폭 6$\sim$7m 는 교통량 1,000vph에서 급격한 지체 시간 상승을 보이고 있으나. 도로폭 10$\sim$11.5m도로는 1.200vph에서 약간의 변화를 보였다. 이 결과(pcu/일)를 국도와 지방도 일평균교통량(대/일)분포와 비교분석 하여 다양한 횡단면 기준을 제시하였다.

• 디지털산업정보학회논문지
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• 제16권2호
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• pp.1-9
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• 2020

Many cryptographic and error control coding algorithms rely on finite field GF(2m) arithmetic. Hardware implementation of these algorithms needs an efficient realization of finite field arithmetic operations. Finite field multiplication is complicated among the basic operations, and it is employed in field exponentiation and division operations. Various algorithms and architectures are proposed in the literature for hardware implementation of finite field multiplication to achieve a reduction in area and delay. In this paper, a low area and delay efficient semi-systolic multiplier over finite fields GF(2m) using the modified Montgomery modular multiplication (MMM) is presented. The least significant bit (LSB)-first multiplication and two-level parallel computing scheme are considered to improve the cell delay, latency, and area-time (AT) complexity. The proposed method has the features of regularity, modularity, and unidirectional data flow and offers a considerable improvement in AT complexity compared with related multipliers. The proposed multiplier can be used as a kernel circuit for exponentiation/division and multiplication.

• Journal of the Optical Society of Korea
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• 제9권2호
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• pp.54-58
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• 2005

A novel mode analysis method and differential mode delay measurement technique for a multimode optical fiber based on optical frequency domain reflectometry has been proposed for the first time. We have used a conventional OFDR with a tunable external cavity laser and a Michelson interferometer. A few-mode optical multimode fiber was prepared to test our proposed measurement technique. The differential mode delay (DMD) of the sample fiber was measured to be 16.58 ps/m with a resolution of 1.5 ps/m. We have also compared the OFDR measurement results with those obtained using a traditional time-domain measurement method.

• Journal of Communications and Networks
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• 제1권3호
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• pp.189-200
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• 1999

For admitting a hard real-time connection to an ATM network, it is required that the end-새둥 delays of cells belong-ing to the connection meet their deadlines without violating the guarantees already provided to the currently active connections. There are two kinds of methods to analyze the end-to-end delay in an ATM network. A decomposed method analyzes the worst case delay for each switch and then computes the total delay as the sum of the delays at individual switches. On the other hand, an integrated method analyzes all the switches involved in an inte-grated manner and derives the total delay directly. In this paper, we present an efficient and effecitive integrated method to compute the end-to-end delay. We evaluate the network performance under different system parameters and we compare the performance of the proposed method with the conventional decomposed and other integrated methods [1], [3], [5]-[9].

• 화약ㆍ발파
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• 제9권4호
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• pp.3-12
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• 1991

The cautious blasting works had been used with emulsion explosion electric M /S delay caps. Drill depth was from 3m to 6m with Crawler Drill 70mm on the calcalious sand stone (soft-moderate-semi hard Rock) . The total numbers of feet blast were 88. Scale distance were induces 15.52-60.32. It was applied to Propagation Law in blasting vibration as follows .Propagtion Law in Blasting Vibration V=k(D/W/sup b/)/sup n/ where V : Peak partical velocity(cm/sec) D : Distance between explosion and recording sites(m) W ; Maximum Charge per delay -period of eight milliseconds or more(Kg) K : Ground transmission constant, empirically determind on the Rocks, Explosive and drilling pattern ets. b : Charge exponents n : Reduced exponents Where the quantity D/W/sup b/ is known as the Scale distance. Above equation is worked by the U.S Bureau of Mines to determine peak particle velocity. The propagation Law can be catagrorized in three groups. Cabic root Scaling charge per delay Square root Scaling of charge per delay Site-specific Scaling of charge delay Charge and reduction exponents carried out by multiple regressional analysis. It's divided into under loom and over loom distance because the frequency is varified by the distance from blast site. Empirical equation of cautious blasting vibration is as follows. Over 30m--under 100m----V=41(D/ W)/sup -1.41/-----A Over l00m---------V=121(D/ W)/sup -1.56/-----B K value on the above equation has to be more specified for furthur understand about the effect of explosives. Rock strength, And Drilling pattern on the vibration levels, it is necessary to carry out more tests.

• 정보처리학회논문지A
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• 제14A권4호
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• pp.203-208
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• 2007

본 논문에서는 CMOS 다치 논리회로를 이용하여 $64{\times}64$ 비트 Modified Booth 곱셈기를 설계하였다. 설계한 곱셈기는 Radix-4 알고리즘을 이용하여 전류모드 CMOS 4치 논리회로로 구현하였다. 이 곱셈기는 트랜지스터 수를 기존의 전압모드 2진 논리 곱셈기에 비해 64.4% 감소하였으며, 내부 구조를 규칙적으로 배열하여 확장성을 갖도록 설계하였다. 설계한 회로는 2.5V의 공급전압과 단위전류 $5{\mu}A$를 사용하여, $0.25{\mu}m$ CMOS 기술을 이용하여 구현하였으며 HSPICE를 사용하여 검증하였다. 시뮬레이션 결과, 2진 논리 곱셈기는 $7.5{\times}9.4mm^2$의 점유면적에 9.8ns의 최대 전달지연시간과 45.2mW의 평균 전력소모 특성을 갖는 반면, 설계한 곱셈기는 $5.2{\times}7.8mm^2$의 점유면적에 11.9ns의 최대 전달지연시간과 49.7mW의 평균 전력소모 특성으로 점유면적이 42.5% 감소하였다.

• 한국전자파학회논문지
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• 제19권6호
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• pp.597-602
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• 2008

본 논문은 고출력 전자파에 따른 CMOS IC 소자의 피해 효과와 회복 시간을 알아보았다. 고출력 전자파 발생 장치는 마그네트론을 사용하였고, CMOS 인버터의 오동작/부동작 판별법은 유관 식별이 가능한 LED 회로로 구성하였다. 그리고 고출력 전자파에 의해 오동작된 CMOS 인버터의 전원 전류와 회복 시간을 관찰하였다. 그 결과, 전계 강도가 약 9.9 kV/m에서의 전원 전류는 정상 전류의 2.14배가 증가하였다. 이는 래치업에 의한 CMOS 인버터가 오작동된 것을 확인할 수 있었다. 또한, COMS 인버터의 파괴는 컴포넌트, 온칩와이어, 그리고 본딩 와이어에서 다른 형태로 관찰하였다 위 실험 결과로, 전자 장비의 고출력 전자파 장해에 대한 이해를 돕는데 기초 자료로 활용될 것으로 예측된다.

• 대한기계학회논문집B
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• 제32권9호
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• pp.720-727
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• 2008

Time delay effects on near-wall turbulent structures are investigated by performing a large-eddy simulation of a transient turbulent flow in a pipe. To elucidate the time delay effects on the near-wall turbulence, we selected the dimensionless acceleration parameter which was used in the previous study. Various turbulent statistics revealed the distinctive features of the delay. It was shown that the dynamic Smagorinsky model is valid to capture the alterations of the turbulence physics well. A dimensionless time for the responses of the flow quantities was introduced to give the detailed information on the delay of the nearwall turbulence. The conditionally-averaged flow fields associated with Reynolds shear stress producing events show that sweep and ejections are closely related to the delays of the turbulence production and the turbulence propagation toward the pipe center. The present study suggested that the enhanced anisotropy of the turbulence in the initial and transient stages would be a challenging problem to standard turbulence models.

• ETRI Journal
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• 제33권4호
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• pp.528-536
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• 2011

In this paper, we analyze the location accuracy of real-time locating systems (RTLSs) in multipath environments in which the RTLSs comply with the ISO/IEC 24730-2 international standard. To analyze the location error of RTLS in multipath environments, we consider a direct path and indirect path, in which time and phase are delayed, and also white Gaussian noise is added. The location error depends strongly on both the noise level and phase difference under a low signal-to-noise ratio (SNR) regime, but only on the noise level under a high SNR regime. The phase difference effect can be minimized by matching it to the time delay difference at a ratio of 180 degrees per 1 chip time delay (Tc). At a relatively high SNR of 10 dB, a location error of less than 3 m is expected at any phase and time delay value of an indirect signal. At a low SNR regime, the location error range increases to 8.1 m at a 0.5 Tc, and to 7.3 m at a 1.5 Tc. However, if the correlation energy is accumulated for an 8-bit period, the location error can be reduced to 3.9 m and 2.5 m, respectively.

• 대한전자공학회논문지
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• 제24권2호
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• pp.254-259
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• 1987

This paper describes the CMOS standard cell library implemented in double metal single poly gate process with 3\ulcornerm design rule, and its results of testing. This standard cell library contains total 33 cells of random logic gates, flip-flop gates and input/output buffers. All of cell was made to have the equal height of 98\ulcornerm, and width in multiple constant grid of 9 \ulcornerm. For cell data base, the electric characteristics of each cell is investigated and delay is characterized in terms of fanout. As the testing results of Ring Oscillator among the cell library, the average delay time for Inverter is 1.05 (ns), and the delay time due to channel routing metal is 0.65(ps)per unit length.