• The Journal of the Acoustical Society of Korea
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• v.16 no.3
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• pp.99-105
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• 1997

This paper analyzes DLL(Delay lock loop) under the multipath fading effects. The evaluated performance measures include the steady-state timing error probability density function (PDF) and the mean-time-to-lose-lock (MTLL) under multipath fading effects. The discriminator characteristic S(${\epsilon}$) is shown to be zero at the point of timing error ${\epsilon}_{0}$ that is not zero, and the MTLL decreases as the delayed signal power $g_{2}$ and delayed time ${\tau}_{d}$ increase. We approximate the steady-state timing error PDF linearly with these variables and evaluate the steady-state timing error PDF and MTLL. The severe multipath fading effects result lower MTLL, in this case we make MTLL larger by increasing the early-late discriminator offset ${\Delta}$. First, we calculate the timing error point ${\epsilon}_{0}$, and present the performance of DLL under multipath fading. The timing error PDF, MTLL and the performance of DLL with ${\Delta}$ are also investigated. And we conclude that the larger ${\Delta}$ makes a higher MTLL and a better performance of DLL under multipath fading effects.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.433-448
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• 2012

A source-synchronous receiver based on a delay-locked loop is presented. It employs a shared global calibration control between channels, yet achieves channel expandability for high aggregate I/O bandwidth. The global calibration control accomplishes skew calibration, equalizer adaptation, and phase lock of all the channels in a calibration period, resulting in the reduced hardware overhead and area of each data lane. In addition, the weight-adjusted dual-interpolating delay cell, which is used in the multiphase DLL, guarantees sufficient phase linearity without using dummy delay cells, while offering a high-frequency operation. The proposed receiver is designed in the 90-nm CMOS technology, and achieves error-free eye openings of more than 0.5 UI across 9-28 inch Nelco4000-6 microstrips at 4-7 Gb/s and more than 0.42 UI at data rates of up to 9 Gb/s. The data lane occupies only $0.152mm^2$ and consumes 69.8 mW, while the rest of the receiver occupies $0.297mm^2$ and consumes 56.0 mW at the 7- Gb/s data-rate and supply voltage of 1.35 V.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.5
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• pp.459-464
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• 2013

A reset-free anti-harmonic programmable multiplying delay-locked loop (MDLL) that provides flexible integer clock multiplication for high performance clocking applications is presented. The proposed MDLL removes harmonic locking problems by utilizing a simple harmonic lock detector and control logic, which allows this MDLL to change the input clock frequency and multiplication factor during operation without the use of start-up circuitry and external reset. A programmable voltage controlled delay line (VCDL) is utilized to achieve a wide operating frequency range from 80 MHz to 1.2 GHz with a multiplication factor of 4, 5, 8, 10, 16 and 20. This MDLL achieves a measured peak-to-peak jitter of 20 ps at 1.2 GHz.

• Journal of Satellite, Information and Communications
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• v.6 no.1
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• pp.68-74
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• 2011

In this paper, we present the enhancement results such as availability and accuracy using the GPS L1 and Galileo E1 signal combination. To enhance the acquisition and tracking performance of signal processing in GNSS receiver. several tracking loops with integrator, discriminator, and loop filter module are applied. Also, this paper presents the performance comparison results between prototype receiver equipped with hardware board and software receiver. Also the tracking loop performance of real hardware receiver is verified by comparing with tracking accuracy, sensitivity occurred by the Spirent simulator. Especially, to process the Galileo E1 signal, it is used the a power early late type which is the typical type for DLL discriminator.

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.353-356
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• 1999

A 3.3V PLL(Phase Locked loop) is designed for a high frequency, low voltage, and low power applications. This paper proposes a new PLL architecture to improve voltage to frequency linearity of VCO(Voltage controlled oscillator) with new delay cell. The proposed VCO operates at a wide frequency range of 30MHz~1㎓ with a good linearity. The DC-DC voltage up/down converter is utilized to regulate the control voltage of the two-stage VCO. The designed PLL architecture is implemented on a 0.6${\mu}{\textrm}{m}$ n-well CMOS process. The simulation results show a locking time of 2.6$\mu$sec at 1Hz, Lock in range of 100MHz~1㎓, and a power dissipation of 112㎽.

• Proceedings of the KIEE Conference
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• 2002.07d
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• pp.2637-2639
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• 2002

This paper presents the design and implementation of a baseband Modem using DSP that supports a wireless LAN. It is implemented with DSP and D/A and A/D Converters in baseband and tested without using IF and RF modules. In this paper, we have used the matched filler and DLL(delay lock loop) for synchronization. And the matched filter and the carrier recovery are directly connected. Therefore, the proposed architecture is very simple and the operation of DSP becomes fast.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.963-964
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• 2006

By combining a digital DLL and an analog DLL in 2-stage, an improved DLL is implemented in this paper. The proposed DLL is composed of a RDLL (Register Controlled DLL) and a conventional analog DLL. The phase comparator used in the DLL is built with sense-amp based D flip-flops for high speed operation. The proposed DLL circuits have been designed, simulated in 0.18um, 1.8V TSMC CMOS library. The implemented DLL have demonstrated the fast lock-on time of 1us and low jitter of 72ps.

• Proceedings of the IEEK Conference
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• 2007.07a
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• pp.71-72
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• 2007

대역 제한된 DS/SS 시스템의 상관 함수는 최고 값이 나타나는 시점과 함께 이른 또는 늦은 상관시간 옵셋 영역에서 극소 또는 극대로 나타나는 시점을 특징점으로 갖는다. 이 가운데 이른 상관시간옵셋 영역의 상관 함수는 다중경로 신호에 의해 덜 왜곡되기 때문에 이 영역의 상관 함수를 이용해 부호 동기를 추적하여 유지할 수 있다면 EL-DLL (delay lock loop with early minus late discriminator) 보다 추적편이를 줄일 수 있다. 본 논문에 이런 특성을 이용하는 추적편이 완화 기법을 제안하고, 모의실험을 통해 성능을 알아본다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.23-30
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• 2005

This paper describes a DLL(delay locked loop)-based multi-clock generator having the lower active stand-by power as well as a fast relocking after re-activating the DLL. for low power and high speed VLSI chip. It enables a frequency multiplication using frequency multiplier scheme and produces output clocks with 50:50 duty-ratio regardless of the duty-ratio of system clock. Also, digital control scheme using DAC enables a fast relocking operation after exiting a standby-mode of the clock system which was obtained by storing analog locking information as digital codes in a register block. Also, for a clock multiplication, it has a feed-forward duty correction scheme using multiphase and phase mixing corrects a duty-error of system clock without requiring additional time. In this paper, the proposed DLL-based multi-clock generator can provides a synchronous clock to an external clock for I/O data communications and multiple clocks of slow and high speed operations for various IPs. The proposed DLL-based multi-clock generator was designed by the area of $1796{\mu}m\times654{\mu}m$ using $0.35-{\mu}m$ CMOS process and has $75MHz\~550MHz$ lock-range and maximum multiplication frequency of 800 MHz below 20psec static skew at 2.3v supply voltage.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.33 no.1C
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• pp.86-93
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• 2008

The Galileo system, a global navigation satellite system(GNSS) developed by E.U., uses the direct sequence/spread spectrum(DS/SS) modulation. A DS/SS-based system performs a fine synchronization between the received and locally generated spreading signals, via attacking process. In the absence of multipath signals, using the symmetric characteristic of the correlation function, the delay lock loop with the early minus late discriminator(EL-DLL) offers the best performance in tracking. However, in the presence of multipath signals, the symmetry of the correlation function could be lost, causing a tracking bias. In this paper, we observe that the correlation values in the advanced offset range remain almost unchanged, due to the multipath signals being received later than a line-of-sight signal. Based on this observation, we propose a novel tracking scheme for a Galileo BOC(1,1) system.