• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2004.05b
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• pp.583-586
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• 2004

In this paper, we have analyzed the performance of synchronization of CCK(Complementary Code Keying) modulation scheme used for IEEE 802.11g wireless LAM system supporting 54 Mbps of high speed data rate over 2.4 GHz. At receiver, the clock frequency offset is caused by noise or fading. This frequency error occurs the offset of clock timing and causes ISI. Therefore the tracking is required to reduce the clock timing offset. The DLL(Delay Lock Loop), asychronization mode, performing tacking the clock is used for the simulation. The simulation result shows jitter variance and BER performance in the AWGN and multipath fading channel environment.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.694-701
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• 2011

This paper addresses a synchronization technique based on an adaptive combining of the sub-correlation functions obtained from multiband sine phased binary offset carrier (BOC) signals, allowing a BOC signal receiver to deal with multiband sine phased BOC signals. Specifically, we first obtain the sub-correlation functions composing the BOC autocorrelation function, and then, re-combine the sub-correlation functions generating a correlation function with no side-peak. Finally, by replacing the BOC autocorrelation with the correlation function with no side-peak in the delay lock loop, the proposed scheme performs unambiguous signal tracking. The proposed synchronization scheme is applicable to generic sine phased BOC signals. Numerical results demonstrate that the proposed scheme provides a performance improvement over the conventional unambiguous schemes in terms of the tracking error standard deviation.

• Journal of information and communication convergence engineering
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• v.3 no.3
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• pp.142-145
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• 2005

In this paper, a new programmable DLL (delay locked loop) based clock synthesizer is proposed. DLL has several inherent advantages, such as no phase accumulation error, fast locking and easy integration of the loop filter. This paper proposes a new programmable DLL that includes a PFD(phase frequency detector), a LSI(lock status indicator), and a VCDL(voltage controlled delay line) to generate multiple clocks. It can generate clocks from 3 to 9 times of input clock with $2{\mu}s$ locking time. The proposed DLL operating in the frequency range of 300MHZ-900MHz is verified by the HSPICE simulation with a $0.35{\mu}m$ CMOS process.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.22 no.3
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• pp.506-514
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• 1997

In this paper, we implement digital circuit of despreading delay lock loop for GPS receiver. The designed system consists of Epoch signal generator, two 13bit correlators which correlates the received C/A code and the locally generated C/A code in the receiver, the C/A code generator which generates C/A code of selected satellite, and the direct digital clock synthesizer which generates the clock of the C/A code generator to control the phase and clock rate, the clock controller, and the clock divider. The designed circuit has the function of the acquisition and tracking by the autocorrelation characteristics of Gold code. The controller generates each other control signals according to the correlation value. The designed circuit is simulated to verify the logic functional performance. By using the simulator STR-2770 that generates the virtual GPS signal, the deigned FPGA chip is verified the circuit performance.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.264-269
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• 2006

A $0.12GHz{\sim}1.4GHz$ DLL-based clock generator with the capability of multiplied four phase clock generation was designed using a 0.18um CMOS process. An adaptive bandwidth DLL with a regulated supply delay line was used for a multiphase clock generation and a low jitter. An extra phase detector (PD) in a reference DLL solves the problem of the initial VCDL delay and achieves a fast lock time. Twice multiplied four phase clocks were generated at the outputs of four edge combiners, where the timing alignment was achieved using a coarse lock signal and the 10 multiphase clocks with T/8 time difference. Those four clocks were combined one more time using a static XOR circuit. Therefore the four times multiplication was achieved. With a 1.8V supply, the rms jitter of 2.1ps and the peak-to-peak jitter of 14.4ps were measured at 1.25GHz output. The operating range is $0.12GHz{\sim}1.4GHz$. It consumes 57mW and occupies 450*325um2 of die area.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.4
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• pp.9-21
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• 2008

In this paper, we propose a GNSS-based RF receiver, A high precision localization architecture, and a high sensitivity localization architecture in order to solve the satellite navigation system's problem mentioned above. The GNSS-based RF receiver model should have the structure to simultaneously receive both the conventional GPS and navigation information data of future-usable Galileo. As a result, it is constructed as the multi-band which can receive at the same time Ll band (1575.42MHz) of GPS and El band (1575.42MHz), E5A band (1207.1MHz), and E4B band (1176.45MHz) of Galileo This high precision localization architecture proposes a delay lock loop with the structure of Early_early code, Early_late code, Prompt code, Late_early code, and Late_late code other than Early code, Prompt code, and Late code which a previous delay lock loop structure has. As we suggest the delay lock loop structure of 1/4chips spacing, we successfully deal with the synchronization problem with the C/A code derived from inaccuracy of the signal received from the satellite navigation system. The synchronization problem with the C/A code causes an acquisition delay time problem of the vehicle navigation system and leads to performance reduction of the receiver. In addition, as this high sensitivity localization architecture is designed as an asymmetry structure using 20 correlators, maximizes reception amplification factor, and minimizes noise, it improves a reception rate. Satellite navigation system repeatedly transmits the same C/A code 20 times. Consequently, we propose a structure which can use all of the same C/A code. Since this has an adaptive structure and can limit(offer) the number of the correlator according to the nearby environment, it can reduce unnecessary delay time of the system. With the use of this structure, we can lower the acquisition delay time and guarantee the continuity of tracking.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.44 no.4
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• pp.324-332
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• 2016

In this paper, the terminal homing loop with a IIR-type strapdown seeker and a roll rate gyroscope is proposed. Basically, the proposed homing loop is based on the look-angle-control guidance. Since the range of the seeker is strictly limited, the missile is delivered to a point to lock the target on the seeker via non-guided flight during the midcourse guidance. The non-standard firing table is developed to compensate the wind and the target movement. To secure the delay margin is very important to prevent the instability of the homing loop when the time delay of the seeker is included. To validate the proposed homing loop, the 6-DOF nonlinear simulation is performed, and the Monte-Carlo simulation is also done for checking the robustness for the various kinds of uncertainty.

• Journal of Satellite, Information and Communications
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• v.5 no.1
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• pp.54-57
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• 2010

The navigation system like GPS which is core technology is based on Code Division Multiple Access(CDMA) techniques. To receive satellite signal smoothly in CDMA, received signals have to synchronize with spread code. In this paper, we focus on the code tracking methods among synchronization techniques. The conventional delay lock loop(DLL) is unsuitable for multi-path channel. We will introduce how it overcomes distortion by multi-path. We will propose method that separates out multi-path signals and tracks the each path signals. And we will confirm performance of proposed method using Spirent simulator.

• Proceedings of the IEEK Conference
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• 2000.11b
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• pp.83-86
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• 2000

This paper describes a delay-locked loop(DLL_) with low-jitter using Vernier Method. This DLL can be used to synchronize the internal clock to the external clock with very short time interval and fast lock-on. The proposed circuit was simulated in a 0.25 $\mu\textrm{m}$ CMOS technology to realize low-jitter. We verified 50-ps of time interval within 5 clock cycles of the clock as the simulation results.

• Journal of Satellite, Information and Communications
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• v.4 no.2
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• pp.39-45
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• 2009

This paper proposes the specific code synchronization technique for DS-SS(Direct Sequence-Spread Spectrum transmission in the DVB-RCS +M standard. DS-SS is better than multi-carrier transmission method under nonlinear channel but imposes a long acquisition time. To improve the synchronization aspect, the robust correlation structure is introduced for acquisition and the nonlinear delay lock loop is done for tracking. MAT(Mean Acquisition Time) performances is shown to validate its superiority. In addition, code tracking and jitter performances are done when code tracking algorithm based on 2 oversamples which is not influenced by sampling clock timing offset and carrier freq. offset is used.