• Current Applied Physics
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• v.18 no.11
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• pp.1447-1450
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• 2018

The electron spin resonance (ESR) detects point defect of the In-Ga-Zn oxide (IGZO) like singly ionized oxygen vacancies and excess oxygen, and get spin density as a parameter of defect state. So, we demonstrated the spin density measurement of the IGZO film with various deposition conditions and it has linear relationship. Moreover, we matched the spin density with the total BTS and the threshold voltage ($V_{th}$) distribution of the IGZO thin film transistors. The total BTS ${\Delta}V_{th}$ and the $V_{th}$ distribution were degraded due to the spin density increases. The spin density is the useful indicator to predict $V_{th}$ instability of IGZO TFTs.

• 한국연소학회:학술대회논문집
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• 2005.10a
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• pp.328-336
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• 2005

Effects of surface defect distribution on flame instability during flame-surface interaction are experimentally investigated. To examine the chemical quenching phenomenon, we prepared thermally grown silicon oxide plates with well-defined defect density. Ion implantation was used to control the number of defects, i.e. oxygen vacancies. In an attempt to preferentially remove the oxygen atoms from silicon dioxide surface, argon ions with low energy level from 3keV to 5keV were irradiated at the incident angle of $60^{\circ}C$. Compositional and structural modification of $SiO_2$ induced by low-energy $Ar^+$ ion irradiation has been characterized by Atomic Force Microscopy (AFM) and X-ray Photoelectron Spectroscopy (XPS). The analysis shows that as the ion energy increases, the number of structural defect also increases and non-stoichiometric condition of $SiO_x(x{\le}2)$ plates is enhanced. From the quenching distance measurements, we found out that when the surface temperature is under $300^{\circ}C$, the quenching distance decreases on account of reduced heat loss; as the surface temperature increases over $300^{\circ}C$, however, quenching distance increases despite reduced heat loss effect. Such aberrant behavior is caused by heterogeneous chemical reaction between active radicals and surface defect sites. The higher defect density, the larger quenching distance. This results means that chemical quenching is governed by radical adsorption and can be parameterized by the oxygen vacancy density on the surface.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2001.05b
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• pp.46-49
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• 2001

To estimate the influence of electrical properties due to the poly back seal(PBS). we were investigated defect density in surface by deposition thickness and breakdown voltage in specimens. Deposition thickness of specimen is prepared from 7,000[$\AA$] to 13,000[$\AA$], respectively. From the results, it is confirmed that PBS deposition thickness of 10,000[$\AA$] among the specimen is decreased defect density by contribution of the gettering effect.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.30A no.2
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• pp.46-52
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• 1993

The estimation of yield for semiconductor devices requires not only establishment of critical area but also a new parameter of process defect density that contains inspection mean defect density related cleanness of manufacure process line, minimum feature size and the total number of mask process. We estimate the repaired yield of memory devide, leads the semiconductor technique, repaired by redundancy scheme in relation with defect density distribution function, and we confirm the repaired yield for different devices as this model. This shows the possibility of the yield estimation as statistical analysis for the condition of device related cleanness of manufacture process line, design and manufacture process.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1994.11a
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• pp.54-58
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• 1994

H$_2$ bake and GeH$_4$ clean are used as a in-situ pre-clean method in low temperature Si based epitaxial growth technology using rapid thermal processing chemical vapor deposition (RTPCVD). In this paper, the H$_2$ bake and GeH$_4$ clean processes are optimized for low surface defect density using Taguchi method. In H$_2$ bake process, the epitaxial growth temperature affects dominantly on the surface defect density, and the next affecting factors are H$_2$ bake temperature and rinse time in de-ionised water. In GeH$_4$ clean process, GeH$_4$ clean temperature affects most strongly on the surface defect density, and the minor factor is GeH$_4$flow rate. The optimum process conditions predicted fly Taguchi method agree well with tile experimental data in both in-situ clean processes.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.26 no.3
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• pp.121-125
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• 2016

The effect of temperature and pressure in the nitrogen ambient furnace on bulk micro defect (BMD) and denuded zone (Dz) is experimentally investigated. It is found that as pressure increases, Dz depth increases with a small decrease of BMD density in the range of temperature, $100{\sim}300^{\circ}C$. BMD density with hot isostatic pressure treatment (HIP) at temperature of $850^{\circ}C$ is higher than that without HIP while Dz depth is lower due to much higher BMD density. As the pressure increases, BMD density is increased and saturated to a critical value, and Dz depth increases even if BMD density is saturated. The concentration of nitrogen increases near the surface with increasing pressure, and the peak of the concentration moves closer to the surface. The nitrogen is gathered near the surface, and does not become in-diffusion to the bulk of the wafer. The silicon nitride layer near the surface prevents to inject the additional nitrogen into the bulk of the wafer across the layer. The nitrogen does not affect the formation of BMD. On the other hand, the oxygen is moved into the bulk of the wafer by increasing pressure. Dz depth from the surface is extended into the bulk because the nuclei of BMD move into the bulk of the wafer.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07a
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• pp.424-427
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• 2003

We have investigated the microstructural analysis of epitaxial lateral overgrowth (ELO), pendeoepitaxy (PE), and superlattice structures used as technology for the reduction of structural defects like dislocation in nitride semiconductors using transmission electron microscopy. We confirmed that the regrowth process such as ELO and PE is very effective technique on the reduction of threading dislocation (less than $10^6/cm^2$) in the specific area. However, to decrease the defect density in the whole nitride films and the suppress the generation of defect by regrowth, we should find the optimized conditions. Besides, the process using double PE and AlGaN/GaN superlattice structure showed no effect on the defect reduction up to now.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.10
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• pp.451-457
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• 2003

The silicon wafer is stable status at room temperature, but it is weak at high temperatures which is necessary for it to be fabricated into a power semiconductor device. During thermal diffusion processing, a high temperature produces a variety thermal stress to the wafer, resulting in device failure mode which can cause unwanted oxide charge or some defect. This disrupts the silicon crystal structure and permanently degrades the electrical and physical characteristics of the wafer. In this paper, the electrical characteristics of a single oxide layer due to high temperature diffusion process, wafer resistivity and thickness of polyback was researched. The oxide quality was examined through capacitance-voltage characteristics, defect density and BMD(Bulk Micro Defect) density. It will describe the capacitance-voltage characteristics of the single oxide layer by semiconductor process and device simulation.

• Proceedings of the Korean Vacuum Society Conference
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• 1998.02a
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• pp.105-106
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• 1998

Evaluation of def3ects by etch-ppit formation was studied. A NaOH(30 mol%) etchant was found useful for etch-ppit developpment on ZnSe-based eppilayers grown on (001) gaAs. And a H3ppO4(85 mol%) was used in order to developp etch-ppits on GaN-base eppilayers grown on (0001) Al2O3 After etch-ppit formation on the surfsce. Transmission Electron Microscoppy(TEM) was cppmdicted. By etch-ppit developpment and TEM observation we could determine the defect typpes by etch-ppit configurfations and found origin of etch-ppit in the cse of ZnSe-based materials. Based uppon these results we can do defect identification by etch-ppit test simpply. In the case of GaN-based materials we could evaluate nanoppippe density. however high density of threading dislocations in GaN eppilayers were not revealed by etch-ppit developpment. Based uppon these results we can evaluate the nanoppippe density which difficult to evaluate using TEM beacause of its small size(diameter). And at ppresent status direct matching of etch-ppit density to dislocation density would make severe mistake.

• Current Photovoltaic Research
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• v.5 no.2
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• pp.59-62
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• 2017

Surface texturing is affected the uniformity and size of pyramid with saw mark defect density. To analysis the influence of the saw mark defect density, we textured various si wafer. When the texturing process proceeds without the saw mark removal, silicon wafer of low-saw mark defect density showed small pyramid size of $3.5{\mu}m$ with the lowest average value of the reflectance of 10.6%. When texturing carried out after removal of the saw mark using the TMAH solution, we obtained a reflectance of about 11% and the large pyramid size of $5{\mu}m$. As a result, saw mark wafers showed a better pyramid structure than saw mark-free wafer. This result showed that saw mark can take place more smooth etching by the KOH solution and saw mark-free wafer is determined to be a factor that have a higher reflectance and a large pyramid.