• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.5
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• pp.1-7
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• 2002

Deep sub-micron bulk CMOS circuits require gate electrode materials such as metal silicide and titanium silicide for gate oxides. Many authors have conducted research to improve the quality of the sub-micron gate oxide. However, few have reported on the electrical quality and reliability of an ultra-thin gate. In this paper, we will recommend a novel shallow trench isolation structure and a two-step TiS $i_2$ formation process to improve the corner metal oxide semiconductor field-effect transistor (MOSFET) for sub-0.1${\mu}{\textrm}{m}$ VLSI devices. Differently from using normal LOCOS technology, deep sub-micron CMOS devices using the novel shallow trench isolation (STI) technology have unique "inverse narrow-channel effects" when the channel width of the device is scaled down. The titanium silicide process has problems because fluorine contamination caused by the gate sidewall etching inhibits the silicide reaction and accelerates agglomeration. To resolve these Problems, we developed a novel two-step deposited silicide process. The key point of this process is the deposition and subsequent removal of titanium before the titanium silicide process. It was found by using focused ion beam transmission electron microscopy that the STI structure improved the narrow channel effect and reduced the junction leakage current and threshold voltage at the edge of the channel. In terms of transistor characteristics, we also obtained a low gate voltage variation and a low trap density, saturation current, some more to be large transconductance at the channel for sub-0.1${\mu}{\textrm}{m}$ VLSI devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.9
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• pp.729-734
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• 2000

Recently, Very Large Scale Integrated (VLSI) circuit & deep-submicron bulk Complementary Metal Oxide Semiconductor(CMOS) devices require gate electrode materials such as metal-silicide, Titanium-silicide for gate oxides. Many previous authors have researched the improvement sub-micron gate oxide quality. However, few have reported on the electrical quality and reliability on the ultra thin gate oxide. In this paper, at first, I recommand a novel shallow trench isolation structure to suppress the corner metal-oxide semiconductor field-effect transistor(MOSFET) inherent to shallow trench isolation for sub 0.1${\mu}{\textrm}{m}$ gate oxide. Different from using normal LOCOS technology deep-submicron CMOS devices using novel Shallow Trench Isolation(STI) technology have a unique"inverse narrow-channel effects"-when the channel width of the devices is scaled down, their threshold voltage is shrunk instead of increased as for the contribution of the channel edge current to the total channel current as the channel width is reduced. Secondly, Titanium silicide process clarified that fluorine contamination caused by the gate sidewall etching inhibits the silicidation reaction and accelerates agglomeration. To overcome these problems, a novel Two-step Deposited silicide(TDS) process has been developed. The key point of this process is the deposition and subsequent removal of titanium before silicidation. Based on the research, It is found that novel STI structure by the SEM, in addition to thermally stable silicide process was achieved. We also obtained the decrease threshold voltage value of the channel edge. resulting in the better improvement of the narrow channel effect. low sheet resistance and stress, and high threshold voltage. Besides, sheet resistance and stress value, rms(root mean square) by AFM were observed. On the electrical characteristics, low leakage current and trap density at the Si/SiO$_2$were confirmed by the high threshold voltage sub 0.1${\mu}{\textrm}{m}$ gate oxide.

• Proceedings of the Korean Society for Technology of Plasticity Conference
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• 2007.05a
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• pp.417-420
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• 2007

Micro parts are usually used of producing by micro-electro-mechanical systems(MEMS). In this paper, we present some fundamental results concerning on the MEMS, extrusion condition on the micro forming characteristics and new micro forward extrusion machine has been developed. In the first step, we manufactured micro dies in two kinds of sections. One is a circle section, another is a cross section. The process for fabricating micro dies combines a deep UV-lithography, anisotropic etching techniques and metal electroplating with bulk silicon based on Ni with a thickness of $50{\mu}m$. The outer diameter of Ni-micro dies is 3mm and the diameter of extrusion section is $270{\mu}m$ for a cross section, $500{\mu}m$ for a circle section. The low linear density polyethylene(LLEPD) in the shape of a pellet has been used of micro extrusion. The billet was placed in a container manufactured by electric discharge machining and extruded through the micro die by a piezoelectric actuator. The micro extrusion has succeeded in a forming such micro parts as micro bars, micro cross shafts.

• Journal of Sensor Science and Technology
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• v.22 no.1
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• pp.89-94
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• 2013

In this paper, we developed a beam of MEMS probe card using a BeCu sheet. Silicon wafer thickness of $400{\mu}m$ was fabricated by using deep reactive ion etching (RIE) process. After forming through silicon via (TSV), the silicon wafer was bonded with BeCu sheet by soldering process. We made BeCu beam stress-free owing to removing internal stress by using joule heating. BeCu beam was fused by using joule heating caused by high current. The fabricated BeCu beam measured length of 1.75 mm and width of 0.44 mm, and thickness of $15{\mu}m$. We measured fusing current as a function of the cutting planes. Maximum current was 5.98 A at cutting plane of $150{\mu}m^2$. The proposed low-cost and simple fabrication process is applicable for producing MEMS probe beam.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.08a
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• pp.382-382
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• 2012

Nanostructures have a larger surface/volume ratio as well as unique mechanical, physical, chemical properties compared to existing bulk materials. Materials for biomedical implants require a good biocompatibility to provide a rapid recovery following surgical procedure and a stabilization of the region where the implants have been inserted. The biocompatibility is evaluated by the degree of the interaction between the implant materials and the cells around the implants. Recent researches on this topic focus on utilizing the characteristics of the nanostructures to improve the biocompatibility. Several studies suggest that the degree of the interaction is varied by the relative size of the nanostructures and cells, and the morphology of the surface of the implant [1, 2]. In this paper, we fabricate the nanowires on the Ti substrate for better biocompatible implants and other biomedical applications such as artificial internal organ, tissue engineered biomaterials, or implantable nano-medical devices. Nanowires are fabricated with two methods: first, nanowire arrays are patterned on the surface using e-beam lithography. Then, the nanowires are further defined with deep reactive ion etching (RIE). The other method is self-assembly based on vapor-liquid-solid (VLS) mechanism using Sn as metal-catalyst. Sn nanoparticle solutions are used in various concentrations to fabricate the nanowires with different pitches. Fabricated nanowries are characterized using scanning electron microscopy (SEM), x-ray diffraction (XRD), and high resolution transmission electron microscopy (TEM). Tthe biocompatibility of the nanowires will further be investigated.

• Current Photovoltaic Research
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• v.4 no.1
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• pp.12-15
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• 2016

Screen printing technique followed by firing has commonly been used as metallization for both laboratory and industrial based solar cells. In the solar cell industry, the firing process is usually conducted in a belt furnace and needs to be optimized for fabricating high efficiency solar cells. The printed-Al layer on the silicon is rapidly heated at over $800^{\circ}C$ which forms a layer of back surface field (BSF) between Si-Al interfaces. The BSF layer forms $p-p^+$ structure on the rear side of cells and lower rear surface recombination velocity (SRV). To have low SRV, deep $p^+$ layer and uniform junction formation are required. In this experiment, firing process was carried out by using conventional tube furnace with $N_2$ gas atmosphere to optimize $V_{oc}$ of laboratory cells. To measure the thickness of BSF layer, selective etching was conducted by using a solution composed of hydrogen fluoride, nitric acid and acetic acid. The $V_{oc}$ and pseudo efficiency were measured by Suns-$V_{oc}$ to compare cell properties with varied firing condition.

• Laser Solutions
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• v.13 no.4
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• pp.7-13
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• 2010

Today, the most common process for generating Through Silicon Vias (TSVs) for 3D ICs is Deep Reactive Ion Etching (DRIE), which allows for high aspect ratio blind holes with low surface roughness. However, the DRIE process requires a vacuum environment and the use of expensive masks. The advantage of using lasers for TSV drilling is the higher flexibility they allow during manufacturing, because neither vacuum nor lithography or masks arc required and because lasers can be applied even to metal and to dielectric layers other than silicon. However, conventional nanosecond lasers have the disadvantage of causing heat affection around the target area. By contrast, the use of a picosecond laser enables the precise generation of TSVs with less heat affected zone. In this study, we conducted a comparison of thermalization effects around laser-drilled holes when using a picosecond laser set for a high pulse energy range and a low pulse energy range. Notably, the low pulse energy picosecond laser process reduced the experimentally recast layer, surface debris and melts around the hole better than the high pulse energy process.

• Transactions on Electrical and Electronic Materials
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• v.15 no.2
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• pp.91-95
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• 2014

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{\times}1.04{\times}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{\times}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.15 no.11
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• pp.958-962
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• 2002

This paper reports on the fabrication of free-standing microstructures by DRIE (deep reactive ion etching). SOI (Si-on-insulator) structures with buried cavities are fabricated by SDB (Si-wafer direct bonding) technology and electrochemical etch-stop. The cavity was formed the upper handling wafer by Si anisotropic etch technique. SDB process was performed to seal the formed cavity under vacuum condition at -760 mmHg. In the SDB process, captured air and moisture inside of the cavities were removed by making channels towards outside. After annealing (100$0^{\circ}C$, 60 min.), the SDB SOI structure with a accurate thickness and a good roughness was thinned by electrochemical etch-stop in TMAH solution. Finally, it was fabricated free-standing microstructures by DRIE. This result indicates that the fabrication technology of free-standing microstructures by combination SDB, electrochemical etch-stop and DRIE provides a powerful and versatile alternative process for high-performance bulk micromachining in MEMS fields.

• Proceedings of the KIEE Conference
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• 1998.07d
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• pp.1549-1551
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• 1998

We have designed and developed narrow bandpass multipole filters for satellite communication using $YBa_2Cu_3O_{7-x}$(YBCO) thin films on MgO substrates. The superconducting film used in this study was prepared by laser ablation on one side polished MgO (100) substrates. A Nd:YAG laser was used to fabricate YBCO thin films. The wave length of the laser was 355 nm. The laser beam was focused onto a YBCO target rotating linearly to avoid deep craters that may eject macroscopic YBCO particles. The YBCO films were grown at $750^{\circ}C$ in the oxygen partial pressure of 200 mTorr. The deposited YBCO thin films were patterned by conventional wet-etching method. The transition temperatures of YBCO thin films were 85 - 88 K and the film thicknesses were about 5,000 $\AA$. By comparing the performances of normal-metal filters and YBCO filters, we observed that superconducting YBCO multipole filters have been showed superior performances at 77 K.