• 대한전자공학회논문지SD
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• 제42권9호
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• pp.61-72
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• 2005

본 논문에서는 평면계획 단계에서 모듈의 전원 잡음을 줄이기 위해 필요한 decoupling capacitance를 효과적으로 할당하는 방법을 제시한다. 먼저, 각 모듈의 decoupling capacitance가 과대평가되고 추가 면적 삽입으로 모듈의 전원 잡음이 변하는 기존 접근 방법의 문제점을 살펴보고, 이를 해결할 수 있는 새로운 방법을 제시한다. 또한, 선형프로그래밍 방법보다 빠른 시간 내에 decoupling capacitance 면적을 위한 빈 공간을 할당하는 간단한 휴리스틱 방법을 제안한다. 실험결과에서 제시된 방법은 Zhao[4]의 방법과 비교하여 decoupling capacitance 면적이 평균 $7.9\%$ 감소하고, 이로 인해 평면계획 결과의 전체 면적과 와이어 길이가 감소하였다. 또한, 추가 면적 삽입으로 인한 모듈의 전원 잡음 문제를 잘 해결하고 있음을 확인하였다. 수행시간 비교에서는 평균 $11.6\%$의 향상을 보였다.

• 전력전자학회논문지
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• 제24권3호
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• pp.181-190
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• 2019

Active power decoupling circuits have emerged to eliminate the inherent second-order ripple power in a single-phase power conversion system. This study proposes a design method to determine the optimal capacitance for active power decoupling circuits to achieve high power density. Minimum capacitance is derived by analyzing ripple power in a passive power decoupling circuit, a buck-type circuit, and a capacitor-split-type circuit. Double-frequency ripple power decoupling capabilities are also analyzed in three decoupling circuits under a 3.3 kW load condition for a battery charger application. To verify the proposed design method, the performance of the three decoupling circuits with the derived minimum capacitance is compared and analyzed through the results of MATLAB -Simulink and hardware-in-the-loop simulations.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 추계학술대회 논문집
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• pp.137-138
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• 2012

In this paper, three-port flyback inverter with Active Power Decoupling(APD) circuit is analyzed. Conventional flyback inverter with passive power decoupling circuit needs the electrolytic capacitor with large capacitance for decoupling between constant DC power and instantaneous AC power. However the electrolytic capacitor has low lifespan about 50000 to 100000 hours. So the active power decoupling techniques are applied to reduce input capacitance of flyback inverter. Thus the overall system can achieve smaller size and longer lifespan. Proposed three-port flyback inverter is verified by design optimization, simulation and experimental result.

• Journal of Power Electronics
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• 제13권4호
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• pp.558-568
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• 2013

In this paper, a new decoupling technique for a flyback inverter using an active power decoupling circuit with auxiliary winding and a novel switching pattern is proposed. The conventional passive power decoupling method is applied to control Maximum Power Point Tracking (MPPT) efficiently by attenuating double frequency power pulsation on the photovoltaic (PV) side. In this case, decoupling capacitor for a flyback inverter is essentially required large electrolytic capacitor of milli-farads. However using the electrolytic capacitor have problems of bulky size and short life-span. Because this electrolytic capacitor is strongly concerned with the life-span of an AC module system, an active power decoupling circuit to minimize input capacitance is needed. In the proposed topology, auxiliary winding defined as a Ripple port will partially cover difference between a PV power and an AC Power. Since input capacitor and auxiliary capacitor is reduced by Ripple port, it can be replaced by a film capacitor. To perform the operation of charging/discharging decoupling capacitor $C_x$, a novel switching sequence is also proposed. The proposed topology is verified by design analysis, simulation and experimental results.

• Journal of Electrical Engineering and Technology
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• 제13권2호
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• pp.677-687
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• 2018

This paper presents a novel power decoupling control scheme with the bidirectional buck-boost converter for primary-side regulation photovoltaic (PV) micro-inverter. With the proposed power decoupling control scheme, small-capacitance film capacitors are used to overcome the life-span and reliability limitations of the large-capacitance electrolytic capacitors. Then, an improved flyback PV inverter is employed in continuous conduction mode with primary-side regulation for the PV power conditioning. The proposed power-decoupling controller shares the reference for primary side current regulation of the flyback PV inverter. The decoupling controller shapes the input current of the bidirectional buck-boost converter. The shared reference eliminates the phase-delay between the input current to the bidirectional buck-boost converter and the double frequency current at the PV primary current. The elimination of the phase-delay in dynamic response enhances the ripple rejection capability of the power decoupling buck-boost converter even with small film capacitor. With proposed power decoupling control scheme, the additional advantage of the primary-side regulation of flyback PV inverter is that there is no need to have an extra current sensor for obtaining the ripplecurrent reference of the decoupling current-controller of the power-decoupling buck-boost converter. Therefore, the proposed power decoupling control scheme is cost-effective as well as the size benefit. A new transient analysis is carried out which includes the source voltage dynamics instead of considering the source voltage as a pure voltage source. For verification of the proposed control scheme, simulation and experimental results are presented.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 전력전자학술대회 논문집
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• pp.486-487
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• 2012

In this paper, novel three-port active power decoupling (APD) method for applying 250[W] micro-inverter. This type using third port for active power decoupling stores the surplus energy and supplies sufficient energy to grid. Conventional decoupling circuit is applied in single phase grid connected micro-inverter especially single-stage configuration like flyback-type DC-AC inverter. In this passive power decoupling method, electrolytic capacitor with large capacitance is needed for decoupling from constant DC power and instantaneous AC power. However the decoupling capacitor is replaced with film capacitor by using APD, thus the overall system can achieve smaller size and long lifespan. Proposed three-port flyback inverter is verified by design and simulation.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2007년도 하계종합학술대회 논문집
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• pp.437-438
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• 2007

In this paper a embedded decoupling capacitor design with gap structure will be discussed. A novel structure is modeling and analization by High Frequency Structure Simulator (HFSS). Proposed capacitor have $2m{\times}2m$ in rectangular shape. The film thickness of copper/dielectric film/substrate is respectively 35um/20um/35um. A dielectric layer of BaTiO3/epoxy has the relative permittivity of 25. Compare of the planar decoupling capacitor, capacitance densities of this structure in the range of $55{\mu}F$/mm2 have been obtained with 50um gap while capacitance densities of planar structure $55{\mu}F$/mm2 in the same size. The frequency dependent behavior of capacitors is numerically extracted over a wide frequency bandwidth 500MHz-7GHz. The decoupling capacitor can work at high frequency band increasing the gap size.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2012년도 추계학술대회 논문집
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• pp.103-104
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• 2012

In the AC module system, mismatch problem between AC power and constant input power is occurred. To solve this problem, electrolytic capacitor is utilized for diminishing power pulsation in PV side. However, it has disadvantages of low life span and weak in temperature. Decoupling method has been studied to reduce the capacitance and replaces electrolytic capacitor to film capacitor. This paper proposes design method for decoupling circuit which bidirectional DC-DC converter using soft switching. Proposed system is verified by design optimization and simulation results.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2017년도 전력전자학술대회
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• pp.246-247
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• 2017

단상 ac/dc, dc/ac 시스템의 경우, ac와 dc사이의 전력 불균형으로 인해 double line frequency ripple power가 발생한다. 이는 harmonic disturbance을 야기시킨다. 일반적으로 전력 리플을 줄이기 위하여 dc-link에 용량이 큰 전해 커패시터를 사용하는데, 용량이 큰 전해 커패시터는 높은 equivalent series resistance(ESR)을 가지며, 상대적으로 짧은 수명을 갖는 한계를 갖는다. 본 논문은 active power decoupling을 추가함으로써 전해 커패시터를 용량이 작은 필름 커패시터로 대체한 회로 구조를 제시한다. 그리고 dc-link 커패시터 선정방법, 설계한 제어기의 성능과 부하 변동에 따른 실험을 PSIM 시뮬레이션으로 확인하고 실험을 통해 검증한다.

• 대한전자공학회논문지SD
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• 제41권1호
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• pp.71-80
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• 2004

본 논문에서는 집적회로 패키지에 기인한 노이즈를 해석할 수 있는 새로운 SSN모델을 보인다. 기존의 디커플링 커패시터를 고려하지 않은 회로모델은 과도하게 SSN을 예측한다는 것을 보였으며, 디커플링 커패시터가 포함된 패키지 회로모델을 통하여 새로운 SSN 모델을 제안하였다. 새롭게 제안된 SSN 모델은 0.18um공정(TSMC 0.18um공정)을 사용하여 다양한$\cdot$회로설계 변수(입력상승시간, 패키지 인덕턴스 및 동시 스위칭 개수)의 변화에 따라 HSPICE 시뮬레이션과 정확히($5\%$ 이내에서) 일치한다는 것을 검증하였다.