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Decoupling Capacitance Allocation at the Floorplan Level for Power Supply Noise Reduction  

Heo Chang-Ryong (Telecommunication Network, Samsung Electronics)
Rim Chong-Suck (Department of Computer Science, Sogang University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SD / v.42, no.9, 2005 , pp. 61-72 More about this Journal
Abstract
This paper proposes a method which efficiently allocates decoupling capacitance to reduce power supply noise at the floorplan level. We observe problems of previous approach that the decoupling capacitance of each module was overestimated and the power supply noises of modules were changed by inserting additional area for decoupling capacitance, and then suggest a new approach. And, we also present a simple heuristic method which can effectively allocate white space modules for decoupling capacitance area within more faster time instead of LP technique. Experimental results show that our approach can reduce the area of decoupling capacitance to average 7.9 percent compared with Zhao's approach in [4]. Therefore both total area and wire length of nniflm result are decreased. Also, we confirm that our approach solves well the problem caused by inserting additional area. In execution time comparison, our approach shows average 11.6 percent improvement.
Keywords
VLSI Design; Power Supply Noise; Decoupling Capacitance; Floorplan;
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