• ETRI Journal
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• v.46 no.3
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• pp.485-500
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• 2024

A hardware architecture is presented to decode (N, K) polar codes based on a low-density parity-check code-like decoding method. By applying suitable pruning techniques to the dense graph of the polar code, the decoder architectures are optimized using fewer check nodes (CN) and variable nodes (VN). Pipelining is introduced in the CN and VN architectures, reducing the critical path delay. Latency is reduced further by a fully parallelized, single-stage architecture compared with the log N stages in the conventional belief propagation (BP) decoder. The designed decoder for short-to-intermediate code lengths was implemented using the Virtex-7 field-programmable gate array (FPGA). It achieved a throughput of 2.44 Gbps, which is four times and 1.4 times higher than those of the fast-simplified successive cancellation and combinational decoders, respectively. The proposed decoder for the (1024, 512) polar code yielded a negligible bit error rate of 10^-4 at 2.7 E_b/N_o (dB). It converged faster than the BP decoding scheme on a dense parity-check matrix. Moreover, the proposed decoder is also implemented using the Xilinx ultra-scale FPGA and verified with the fifth generation new radio physical downlink control channel specification. The superior error-correcting performance and better hardware efficiency makes our decoder a suitable alternative to the successive cancellation list decoders used in 5G wireless communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38B no.2
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• pp.140-145
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• 2013

This paper proposes the high speed LDPC decoder structure base on the DVB-S2. Firstly, We study the solution to avoid the memory conflict. For the high speed decoding process the decoder adapts the HSS(Horizontal Shuffle Scheduling) scheme. Secondly, for the high speed decoding algorithm normalized Min-Sum algorithm is adapted instead of Sum-Product algorithm. And the self corrected is a variant of the LDPC decoding that sets the reliability of a Mc${\rightarrow}$v message to 0 if there is an inconsistency between the signs of the current incoming messages Mv'${\rightarrow}$c and the sign of the previous incoming messages Moldv'${\rightarrow}$c This self-corrected algorithm avoids the propagation on unreliable information in the Tanner graph and thus, helps the convergence of the decoder.Start after striking space key 2 times. Lastly, and this paper propose the optimal hardware architecture supporting the high speed throughput.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.11
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• pp.54-64
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• 2010

Reed-Solomon (RS) codes are the most widely used error correcting codes in digital communications and data storage. Recently, Sudan found algorithm of list decoder for RS codes. List decoder has larger decoding radius than conventional hard-decision decoding algorithms and return more than one candidate polynomial. But, the algorithm includes interpolation and factorization step that demand massive computations. In this paper, an efficient architecture and processing schedule are proposed. The architecture consists of R-MAC, memories, and control unit. The R-MAC computes both of RC and PU steps that are main part of the factorization algorithm. The proposed architecture can achieve higher hardware utilization efficiency (HUE) and throughput by using efficient processing schedule and memory architecture. Also, the architecture can be designed flexibly with scalability for various applications. We design and synthesize our architecture using Dongbu-Anam $0.18{\mu}m$ standard cell library and the maximum clock frequency is 330MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2011.05a
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• pp.132-135
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. To minimize hardware complexity, it adopts a block-serial (partially parallel) architecture based on the layered decoding scheme. A novel memory reduction technique devised using the min-sum decoding algorithm reduces the size of check-node memory by 47% as compared to conventional method. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.

• Journal of Advanced Marine Engineering and Technology
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• v.40 no.6
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• pp.535-541
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• 2016

In this paper, we analyzed efficient decoding scheme with FTN(Faster than Nyquist) method that is transmission method faster than Nyquist theory and increase the throughput. Applying the FTN method to satellite and underwater communication, we proposed an efficient transceiver model. To minimize ISI(Inter-Symbol Interference) induced by FTN signal, turbo equalization algorithms that iteratively exchange probabilistic information between Viterbi equalizer based on BCJR algorithm and LDPC decoder are used in satellite communication. In others, for underwater communication, DFE equalizer and LDPC decoder are concatenated to improve performance.

• Journal of IKEEE
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• v.24 no.1
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• pp.186-193
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• 2020

In this paper, we propose a multi-threading system to support reconfigurable hardware accelerators on Zynq SoC. We implement high-performance JPEG decoder with reconfigurable 2D IDCT hardware accelerators to achieve maximum performance available on the platform. In this system, up to four reconfigurable hardware accelerators synchronized with SW threads can be dynamically reconfigured to provide adaptive computing capabilities according to the given image resolution and the compression ratio. JPEG decoding is operated using images with resolutions 480p, 720p, 1080p at the compression ratio of 7:1-109:1. We show that significant performance improvements are achieved as the image resolution or the compression ratio increase. For 1080p resolution, the performance improvement is up to 79.11 times with throughput speed of 99 fps at the compression ratio 17:1.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.14 no.11
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• pp.4522-4536
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• 2020

Nowadays, cloud is the fastest emerging technology in the IT industry. We can store and retrieve data from the cloud. The most frequently occurring problems in the cloud are security and privacy preservation of data. For improving its security, secret information must be protected from various illegal accesses. Numerous traditional cryptography algorithms have been used to increase the privacy in preserving cloud data. Still, there are some problems in privacy protection because of its reduced security. Thus, this article proposes an ElGamal Elliptic Curve (EGEC) Homomorphic encryption scheme for safeguarding the confidentiality of data stored in a cloud. The Users who hold a data can encipher the input data using the proposed EGEC encryption scheme. The homomorphic operations are computed on encrypted data. Whenever user sends data access permission requests to the cloud data storage. The Cloud Service Provider (CSP) validates the user access policy and provides the encrypted data to the user. ElGamal Elliptic Curve (EGEC) decryption was used to generate an original input data. The proposed EGEC homomorphic encryption scheme can be tested using different performance metrics such as execution time, encryption time, decryption time, memory usage, encryption throughput, and decryption throughput. However, efficacy of the ElGamal Elliptic Curve (EGEC) Homomorphic Encryption approach is explained by the comparison study of conventional approaches.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.9 no.9
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• pp.3276-3292
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• 2015

Relay-assisted D2D communication extends the communication range of the D2D pairs and helps users to form D2D pairs effectively. However, due to the introduction of the multi-hop relaying, the D2D communication has to occupy extra transmission time, which may decrease the efficiency of the communication system. In this paper, we propose a scheme to make node receive D2D signal and BS signal at overlapping time to improve the spectrum efficiency according to ZigZag decoding and successive-interference-cancellation (SIC). In this way, more data can be delivered during the same duration, thus the network throughput can be further improved. Numerical results verify the performance improvement of the proposed scheme when compared with a baseline scheme. Moreover, we expand the proposed scheme from one-hop relay scenario to multi-hop relay scenario.

• IE interfaces
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• v.12 no.1
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• pp.132-142
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• 1999

Two-sided (left- and right-sided) assembly lines in practice can provide several advantages over one-sided lines in terms of the required line length, throughput time, cost of tools and fixtures, and so on. This paper considers two-sided assembly line balancing with the objective of minimizing line length. The balancing problem is more complicated than that of one-sided lines due to sequence-dependency of tasks assigned to a pair of directly facing workstations. This paper shows how genetic algorithm can be used to solve two-sided assembly line balancing. For this, an encoding and a decoding method suitable to the problem are presented. Proper genetic operators and an evalutation function are also employed. Extensive computational experiments are carried out to show the efficacy of the proposed algorithm. The results show that the algorithm is viable and promising in solution quality and computation time.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.15 no.6
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• pp.1355-1362
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• 2011

This paper describes a multi-mode LDPC decoder which supports three block lengths(648, 1296, 1944) and four code rates(1/2, 2/3, 3/4, 5/6) of IEEE 802.11n WLAN standard. Our LDPC decoder adopts a block-serial architecture based on min-sum algorithm and layered decoding scheme. A novel way to store check-node values and parity check matrix reduces the sizes of check-node memory and H-ROM. An efficient scheme for check-node memory addressing is used to achieve stall-free read/write operations. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 219,100 gates and 45,036 bits RAM, and the estimated throughput is about 164~212 Mbps at 50 MHz@2.5v.