• Title/Summary/Keyword: Decoding throughput

Search Result 90, Processing Time 0.027 seconds

LDPC Decoder Architecture for High-speed UWB System (고속 UWB 시스템의 LDPC 디코더 구조 설계)

  • Choi, Sung-Woo;Lee, Woo-Yong;Chung, Hyun-Kyu
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.35 no.3C
    • /
    • pp.287-294
    • /
    • 2010
  • MB-OFDM UWB system will adopt LDPC codes to enhance the decoding performance with higher data rates. In this paper, we will consider algorithm and architecture of the LDPC codes in MB-OFDM UWB system. To suggest the hardware efficient LDPC decoder architecture, LLR(log-likelihood-ration) calculation algorithms and check node update algorithms are analyzed. And we proposed the architecture of LDPC decoder for the high throughput application of Wimedia UWB. We estimated the feasibility of the proposed architecture by implementation in a FPGA. The implementation results show our architecture attains higher throughput than other result of QC-LDPC case. Using this architecture, we can implement LDPC decoder for high throughput transmission, but it is 0.2dB inferior to the BP algorithm.

Design of a Variable Shortened and Punctured RS Decoder (단축 및 펑처링 기반의 가변형 RS 복호기 설계)

  • Song Moon-Kyou;Kong Min-Han;Lim Myoung-Seob
    • The Journal of Korean Institute of Communications and Information Sciences
    • /
    • v.31 no.8C
    • /
    • pp.763-770
    • /
    • 2006
  • In this paper, a variable Reed-Solomon(RS) decoder with erasure decoding functionality is designed based on the modified Euclid's algorithm(MEA). The variability of the decoder is implemented through shortening and puncturing based on the RS(124, 108, 8) code, other than the primitive RS(255, 239, 8) code. This leads to shortening the decoding latency. The decoder performs 4-step pipelined operation, where each step is designed to be clocked by an independent clock. Thus by using a faster clock for the MEA block, the complexity and the decoding latency can be reduced. It can support both continuous- and burst-mode decoding. It has been designed in VHDL and synthesized in an FPGA chip, consuming 3,717 logic cells and 2,048-bit memories. The maximum decoding throughput is 33 MByte/sec.

Throughput Improvement of Adaptive Modulation System with an Efficient Turbo-Coded V-BLAST Technique in each MIMO Channel

  • Ryoo, Sang-Jin;Kim, Seo-Gyun;Na, Cheol-Hun;Hong, Jin-Woo;Hwang, In-Tae
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2008.05a
    • /
    • pp.905-908
    • /
    • 2008
  • In this paper, an Adaptive Modulation (AM) system with an efficient turbo-coded Vertical-Bell-lab Layered Space-Time (V-BLAST) technique is proposed. The proposed decoding algorithm adopts iteratively the extrinsic information from a Maximum a Posteriori (MAP) decoder as a priori probability in the two decoding procedures of the V-BLAST scheme of ordering and slicing. In this analysis, each MIMO channel is assumed to be a part of the system of performance improvement.

  • PDF

An optimization of synchronous pipeline design for IP-based H.264 decoder design (IP기반 H.264 디코더 설계를 위한 동기화 파이프라인 최적화)

  • Ko, Byung-Soo;Kong, Jin-Hyeung
    • Proceedings of the IEEK Conference
    • /
    • 2008.06a
    • /
    • pp.407-408
    • /
    • 2008
  • This paper presents a synchronous pipeline design for IP-based H.264 decoding system. The first optimization for pipelining aims at efficiently resolving the data dependency due to motion compensation/intra prediction feedback data flow in H.264 decoder. The second one would enhance the efficiency of execution per each pipelining stage to explore the optimized latency and stage number. Thus, the 3 stage pipeline of CAVLD&ITQ|MC/IP&Rec.|DF is obtained to yield the best throughput and implementation. In experiments, it is found that the synchronous pipelined H.264 decoding system, based on existing IPs, could deal with Full HD video at 125.34MHz, in real time.

  • PDF

The Combined AMC-MIMO System with Optimal Turbo Coded V-BLAST Technique to Improve Throughput and SNR (전송률 향상 및 SNR 개선을 위한 최적의 터보 부호화된 V-BLAST 기법을 적용한 AMC-MIMO 결합시스템)

  • Ryoo, Sang-Jin;Lee, Kyung-Hwan;Choi, Kwang-Wook;Lee, Keun-Hong;Hwang, In-Tae;Kim, Cheol-Sung
    • Journal of Internet Computing and Services
    • /
    • v.8 no.4
    • /
    • pp.61-70
    • /
    • 2007
  • In this paper, we propose and observe the Adaptive Modulation system with optimal Turbo Coded V-BLAST(Vertical-Bell-lab Layered Space-Time) technique that is applied the extrinsic information from MAP Decoder in decoding Algorithm of V-BLAST: ordering and slicing. And comparing the proposed system with the Adaptive Modulation system using conventional Turbo Coded V-BLAST technique that is simply combined V-BLAST with Turbo Coding scheme, we observe how much throughput performance and SNR has been improved. In addition, we show that the proposed system using STD(Selection Transmit Diversity) scheme results in on improved result, By using simulation and comparing to conventional Turbo Coded V-BLAST technique with the Adaptive Modulation systems, the optimal Turbo Coded V-BLAST technique with the Adaptive Modulation systems has SNR gain over all SNR range and better throughput gain that is about 350Kbps in 11dB SNR range. Also, comparing with the conventional Turbo Coded V-BLAST technique using 2 transmit and 2 receive antennas, the proposed system with STD scheme show that the improvement of maximum throughput is about 1.77Mbps in the same SNR range and the SNR gain is about 5.88dB to satisfy 4Mbps throughput performance.

  • PDF

A High Speed Bit-level Viterbi Decoder

  • Kim Min-U;Jo Jun-Dong
    • Proceedings of the Korea Inteligent Information System Society Conference
    • /
    • 2006.06a
    • /
    • pp.311-315
    • /
    • 2006
  • Viterbi decoder는 크게 BM(Branch metric), ACS(Add-Compare-Select), SM(Survivor Memory) block 으로 구성되어 있다. 이중 ACSU 부분은 고속 데이터 처리를 위한 bottleneck이 되어 왔으며, 이의 해결을 위한 많은 연구가 활발히 진행되어 왔다. look ahead technique은 ACSU를 M-step으로 처리하고 CS(Carry save) number를 사용한 새로운 비교 알고리즘을 제안하여 high throughput을 추구했으며, minimized method는 block processing 방식으로 forward, backward 방향으로 decoding을 수행하여 ACSU 부분의 feedback을 완전히 제거하여 exteremely high throughput 을 추구하고 있다. 이에 대해 look ahead technique 의 기본 PE(Processing Element)를 바탕으로 minimized method 알고 리즘의 core block 을 bit-level 로 구현하였으며 : code converter 를 이용하여 CS number 가운데 redundat number(l)를 제거하여 비교기를 더 간단히 하였다. SYNOPSYS의 Design compiler 와 TSMC 0.18 um library 를 이용하여 합성하였다.

  • PDF

Adaptive Forward Error Correction Scheme for Real-Time Communication in Satellite IP Networks

  • Cho, Sung-Rae
    • KSII Transactions on Internet and Information Systems (TIIS)
    • /
    • v.4 no.6
    • /
    • pp.1116-1132
    • /
    • 2010
  • In this paper, a new forward error correction (FEC) protocol is proposed for point-to-multipoint satellite links. Link-layer error control protocols in point-to-multipoint satellite links impose several problems such as unreliability and receiver-heterogeneity. To resolve the problem of heterogeneous error rates at different receivers, the proposed scheme exploits multiple multicast channels to which each receiver tunes. The more channels a receiver tunes to, the more powerful error correcting capability it achieves. Based on its own channel condition, each receiver tunes to as many channels as it needs, which prevents from receiving unwanted parities. Furthermore, each receiver saves the decoding time, processing overhead, and processing energy. Performance evaluation shows that the proposed scheme guarantees the target PER while saving energy. The proposed technique is highly adaptive to the channel variation with respect to the throughput efficiency, and provides scalable PER and throughput efficiency.

Error Control Scheme for High-Speed DVD Systems

  • Lee, Joon-Yun;Lee, Jae-Jin;Park, Tae-Geun
    • 정보저장시스템학회:학술대회논문집
    • /
    • 2005.10a
    • /
    • pp.103-110
    • /
    • 2005
  • We present a powerful error control decoder which can be used in all of the commercial DVD systems. The decoder exploits the error information from the modulation decoder in order to increase the error correcting capability. We can identify that the modulation decoder in DVD system can detect errors more than $60\%$ of total errors when burst errors are occurred. In results, fur a decoded block, error correcting capability of the proposed scheme is improved up to $25\%$ more than that of the original error control decoder. In addition, the more the burst error length is increased, the better the decoder performance. Also, a pipeline-balanced RSPC decoder with a low hardware complexity is designed to maximize the throughput. The maximum throughput of the RSPC decoder is 740Mbps@100MHz and the number of gate counts is 20.3K for RS (182, 172, 11) decoder and 30.7K for RS (208, 192, 17) decoder, respectively

  • PDF

Forward Error Control Coding in Multicarrier DS/CDMA Systems

  • Lee, Ju-Mi;Iickho Song;Lee, Jooshik;Park, So-Ryoung
    • Proceedings of the IEEK Conference
    • /
    • 2000.07a
    • /
    • pp.140-143
    • /
    • 2000
  • In this paper, forward error control coding in multicarrier direct sequence code division multiple access (DS/CDMA) systems is considered. In order to accommodate a number of coding rates easily and make the encoder and do-coder structure simple, we use the rate compatible punctured convolutional (RCPC) code. We obtain data throughputs at several coding rates and choose the coding rate which has the highest data throughput in the SINR sense. To achieve maximum data throughput, a rate adaptive system using channel state information (the SINR estimate) is proposed. The SINR estimate is obtain by the soft decision Viterbi decoding metric. We show that the proposed rate adaptive convolutionally coded multicarrier DS/CDMA system can enhance spectral efficiency and provide frequency diversity.

  • PDF

Analysis of Whole Transcriptome Sequencing Data: Workflow and Software

  • Yang, In Seok;Kim, Sangwoo
    • Genomics & Informatics
    • /
    • v.13 no.4
    • /
    • pp.119-125
    • /
    • 2015
  • RNA is a polymeric molecule implicated in various biological processes, such as the coding, decoding, regulation, and expression of genes. Numerous studies have examined RNA features using whole transcriptome sequencing (RNA-seq) approaches. RNA-seq is a powerful technique for characterizing and quantifying the transcriptome and accelerates the development of bioinformatics software. In this review, we introduce routine RNA-seq workflow together with related software, focusing particularly on transcriptome reconstruction and expression quantification.