• ETRI Journal
• /
• v.26 no.6
• /
• pp.615-621
• /
• 2004

Next generation mobile communication system, such as IMT-2000, adopts Turbo codes due to their powerful error correction capability. This paper presents a block-wise maximum a posteriori (MAP) Turbo decoding structure with a low memory requirement. During this research, it has been observed that the training size and block size determine the amount of required memory and bit-error rate (BER) performance of the block-wise MAP decoder, and that comparable BER performance can be obtained with much shorter blocks when the training size is sufficient. Based on this observation, a new decoding structure is proposed and presented in this paper. The proposed block-wise decoder employs a decoding scheme for reducing the memory requirement by setting the training size to be N times the block size. The memory requirement for storing the branch and state metrics can be reduced 30% to 45%, and synthesis results show that the overall memory area can be reduced by 5.27% to 7.29%, when compared to previous MAP decoders. The decoder throughput can be maintained in the proposed scheme without degrading the BER performance.

• Asia-pacific Journal of Multimedia Services Convergent with Art, Humanities, and Sociology
• /
• v.4 no.2
• /
• pp.369-378
• /
• 2014

The Reed-Muller code is one of the efficient algorithms for multiple bit error correction, however, its high-computation requirement inherent in the decoding process prohibits its use in practical applications. To solve this problem, this paper proposes a graphics processing unit (GPU)-based parallel error control approach using Reed-Muller R(r, m) coding for real-time wireless communication systems. GPU offers a high-throughput parallel computing platform that can achieve the desired high-performance decoding by exploiting massive parallelism inherent in the algorithm. In addition, we compare the performance of the GPU-based approach with the equivalent sequential approach that runs on the traditional CPU. The experimental results indicate that the proposed GPU-based approach exceedingly outperforms the sequential approach in terms of execution time, yielding over 70× speedup.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.48 no.1
• /
• pp.39-49
• /
• 2011

Turbo code needs long decoding time because of iterative decoding. To communicate with high speed, we have to shorten decoding time and it is possible with parallel process. But memory contention can cause from parallel process, and it reduces performance of decoder. To avoid memory contention, QPP interleaver is proposed in 2006. In this paper, we propose MDF method which is fit to QPP interleaver, and has relatively short decoding time and reduced logic. And introduce the design of MAP decode module using MDF method. Designed decoder is targetted to FPGA of Xilinx, and its throughput is 80Mbps maximum.

• 한국정보통신설비학회:학술대회논문집
• /
• 2009.08a
• /
• pp.314-319
• /
• 2009

In this paper, the network performance of a turbo coded optical code division multiple access (COMA) system with cross-layer, which is between physical and network layers, concept is analyzed and simulated We consider physical and MAC layers in a cross-layer concept. An intensity-modulated/direct-detection (IM/DD) optical system employing pulse position modulation (PPM) is considered In order to increase the system performance, turbo codes composed of parallel concatenated convolutional codes (PCCCs) is utilized. The network performance is evaluated in terms of bit error probability (BEP). From the simulation results, it is demonstrated that turbo coding offers considerable coding gain with reasonable encoding and decoding complexity. Also, it is confirmed that the performance of such an optical COMA network can be substantially improved by increasing the interleaver length and the number of iterations in the decoding process. The results of this paper can be applied to implement the indoor optical wireless LANs.

• The KIPS Transactions:PartA
• /
• v.17A no.6
• /
• pp.275-280
• /
• 2010

In this paper, we discuss and propose an efficiently parallelized block cipher algorithm on the CELL BE processor. With considering the heterogeneous feature of the CELL BE architecture, we apply different encoding/decoding methods to PPE and SPE and improve the throughput. Our implementation was fully tested, with execution results showing achievement of high throughput, capable of supporting as high network speed as 2.59 Gbps. Compared to various parallel implementations on multi-core systems, our approach provides speedup of 1.34 in terms of encoding/decoding speed.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.44 no.2
• /
• pp.6-14
• /
• 2007

In this paper, we propose and observe the Adaptive Modulation system with optimal Turbo Coded V-BLAST (Vertical-Bell-lab Layered Space-Time) technique that is applied the extrinsic information from MAP (Maximum A Posteriori) Decoder in decoding Algorithm of V-BLAST: ordering and slicing. The extrinsic information is used by a priori probability and the system decoding process is composed of the Main Iteration and the Sub Iteration. And comparing the proposed system with the Adaptive Modulation system using conventional Turbo Coded V-BLAST technique that is simply combined V-BLAST with Turbo Coding scheme, we observe how much throughput performance has been improved. In addition, we observe the proposed system using STD (Selection Transmit Diversity) scheme. As a result of simulation, Comparing with the conventional Turbo Coded V-BLAST technique with the Adaptive Modulation systems, the optimal Turbo Coded V-BLAST technique with the Adaptive Modulation systems has better throughput gain that is about 350 Kbps in 11 dB SNR range. Especially, comparing with the conventional Turbo Coded V-BLAST technique using 2 transmit and 2 receive antennas, the proposed system with STD (Selection Transmit Diversity) scheme show that the improvement of maximum throughput is about 1.77 Mbps in the same SNR range.

• Journal of the Institute of Electronics Engineers of Korea SD
• /
• v.45 no.6
• /
• pp.104-110
• /
• 2008

In this paper, a novel 2-level-search sphere decoding algorithm for multiple-input multiple-output (MIMO) detection and its VLSI implementation are presented. The proposed algorithm extends the search space by concurrently performing symbol detection on 2 level of the tree search. Therefore, the possibility of discarding good candidates can be avoided. Simulation results demonstrate the good performance of the proposed algorithm in terms of bit-error-rate (BER). From the proposed algorithm, an efficient very large scale integration (VLSI) architecture which incorporates low-complexity and fixed throughput features is proposed. The proposed architecture supports many modulation techniques such as BPSK, QPSK, 16-QAM and 64-QAM. The sorting block, which occupies a large portion of hardware utilization, is shared for different operating modes to reduce the area. The proposed hardware implementation results show the improvement in terms of area and BER performance compared with existing architectures.

• Journal of Navigation and Port Research
• /
• v.38 no.3
• /
• pp.211-216
• /
• 2014

In this paper, high throughput method is studied to provide floating objects with broadband service as ship by using satellite. In recent, satellite broadcastings standard is based on DVB-S3 for communication service using wireless device on navigation communication by satellite. LDPC codes are iterative coding algorithm proposed in DVB-S3. In this paper, FTN technique is applied to LDPC codes with 8-PSK modulation and then present the method to alleviate performance degradation due to FTN through BICM-ID. BICM-ID is the method to improve performance by calculating a new LLR from hard-decision value of decoder output. DVB-S2 system with 8-PSK modulation and FTN technique based on iterative decoding had a better performance than DVB-S2 with 8-PSK modulation and FTN technique over Gaussian channels.

• Journal of the Institute of Electronics and Information Engineers
• /
• v.50 no.11
• /
• pp.78-89
• /
• 2013

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

• Journal of the Institute of Electronics Engineers of Korea TC
• /
• v.40 no.11
• /
• pp.51-62
• /
• 2003

This paper presents a novel survivor memeory management and decoding techniques with sequential backward state transition control in the trace back Viterbi decoder. The Viterbi algorithm is an maximum likelihood decoding scheme to estimate the likelihood of encoder state for channel error detection and correction. This scheme is applied to a broad range of digital communication such as intersymbol interference removing and channel equalization. In order to achieve the area-efficiency VLSI chip design with high throughput in the Viterbi decoder in which recursive operation is implied, more research is required to obtain a simple systematic parallel ACS architecture and surviver memory management. As a method of solution to the problem, this paper addresses a progressive decoding algorithm with sequential backward state transition control in the trace back Viterbi decoder. Compared to the conventional trace back decoding techniques, the required total memory can be greatly reduced in the proposed method. Furthermore, the proposed method can be implemented with a simple pipelined structure with systolic array type architecture. The implementation of the peripheral logic circuit for the control of memory access is not required, and memory access bandwidth can be reduced Therefore, the proposed method has characteristics of high area-efficiency and low power consumption with high throughput. Finally, the examples of decoding results for the received data with channel noise and application result are provided to evaluate the efficiency of the proposed method.