• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.12C
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• pp.1222-1230
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• 2005

We aim at increasing the throughput of the hybrid automatic retransmission request (HARQ) protocol in Space-Time (ST) coded multi-antenna transmission systems. By utilizing reliability information at the decoder, we obtain an improved probability of successful decoding, which enhances the overall system throughput at low-complexity. Simulations and analytical results demonstrate the performance of our scheme in impulse noise environment as well as AWGN and fading multi-input multi-ouput (MIMO) channels.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.40 no.1
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• pp.36-44
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• 2003

This paper proposes a Viterbi decoding scheme without trace-back operations to reduce the amount of memory storing the survivor path information, and to increase the decoding speed. The proposed decoding scheme is a modified register exchange scheme, and is verified by a simulation to give the same results as those of the conventional decoders. It is compared with the conventional decoding schemes such as the trace-back and the register exchange scheme. The memory size of the proposed scheme is reduced to 1/(5 x constraint length) of that of the register exchange scheme, and the throughput is doubled compared with that of the trace-back scheme. A decoder with a code rate of 2/3, a constraint length, K＝3 and a trace-back depth of 15 is designed using VHDL and implemented in an FPGA. It is also shown that the modified register exchange scheme can be applied to a block decoding scheme.

• Journal of information and communication convergence engineering
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• v.6 no.1
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• pp.1-5
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• 2008

In this paper, we propose and analyze the AMC (Adaptive Modulation and Coding) system with efficient turbo coded V-BLAST (Vertical-Bell-lab Layered Space-Time) technique. The proposed algorithm adopts extrinsic information from a MAP (Maximum A Posteriori) decoder with iterative decoding as a priori probability in two decoding procedures of V-BLAST scheme; the ordering and the slicing. Also, we consider the AMC system using the conventional turbo coded V-BLAST technique that simply combines the V-BLAST scheme with the turbo coding scheme. And we compare the proposed decoding algorithm to a conventional V-BLAST decoding algorithm and a ML (Maximum Likelihood) decoding algorithm. In addition, we apply a STD (Selection Transmit Diversity) scheme to the systems for better performance improvement. Results indicate that the proposed systems achieve better throughput performance than the conventional systems over the entire SNR range. In terms of transmission rate performance, the suggested system is close in proximity to the conventional system using the ML decoding algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38C no.3
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• pp.311-317
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• 2013

In this paper, we proposed high speed LDPC decoding algorithm based on DVB-S2 standard for applying marine communications in order to multimedia transmission. For implementing the high speed LDPC decoder, HSS algorithm which reduce the iteration numbers without performance degradation is applied. In HSS algorithm, check node update units are update at the same time of bit node update. HSS can be accelerated to the decoding speed because it does not need to separate calculation of the bit nodes, However, check node calculation blocks need many clocks because of just one memory is used. Therefore, this paper proposed partial memory structure in order to reduced the delay and high speed decoder is possible. The results of the simulation, when the max number of iteration set to 30 times, decoding throughput of HSS algorithm is 326 Mbit/s and decoding speed of proposed algorithm is 2.29 Gbit/s. So, decoding speed of proposed algorithm more than 7 times could be obtained compared to the HSS algorithm.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.44 no.6 s.360
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• pp.40-47
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• 2007

In this paper, we propose and analyze the Adaptive Modulation System with optimal Turbo Coded V-BLAST(Vertical-Bell-lab Layered Space-Time) technique that adopts the extrinsic information from MAP (Maximum A Posteriori) Decoder with Iterative Decoding as a priori probability in two decoding procedures of V-BLAST; the ordering and the slicing. Also, we consider and compare the Adaptive Modulation System using conventional Turbo Coded V-BLAST technique that is simply combined V-BLAST with Turbo Coding scheme and the Adaptive Modulation System using conventional Turbo Coded V-BLAST technique that is decoded by the ML (Maximum Likelihood) decoding algorithm. We observe a throughput performance and a complexity. As a result of a performance comparison of each system, it has been proved that the complexity of the proposed decoding algorithm is lower than that of the ML decoding algorithm but is higher than that of the conventional V-BLAST decoding algorithm. however, we can see that the proposed system achieves a better throughput performance than the conventional system in the whole SNR (Signal to Noise Ratio) range. And the result shows that the proposed system achieves a throughput performance close to the ML decoded system. Specifically, a simulation shows that the maximum throughput improvement in each MIMO scheme is respectively about 350 kbps, 460 kbps, and 740 kbps compared to the conventional system. It is suggested that the effect of the proposed decoding algorithm accordingly gets higher as the number of system antenna increases.

• Journal of Communications and Networks
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• v.8 no.2
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• pp.212-219
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• 2006

In this paper, a new turbo codes-based hybrid automatic repeat request (TC-HARQ) scheme with segment selective repeat (SSR) is proposed. The main strategy is, upon retransmission, to repeat the data that are most important for the next round of decoding based on the distribution of residual errors after current decoding. The performance in terms of reliability and throughput is analyzed. To adapt to correlated fading channels where an inter-leaver is always employed before transmission, we further modify the SSR strategy so that data having experienced correlated deep fading are selected for retransmission. Finally, this proposed scheme is applied to the wideband code division multiple access (WCDMA) system under frequency selective fading channels. Simulation results demonstrate that in all single and multiple user cases, SSR-based TC-HARQ leads to significant throughput improvement with similar bit error rate (BER) performance as compared to type-I TC-HARQ.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.1
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• pp.24-33
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• 2012

This paper describes a multi-mode LDPC decoder which supports 19 block lengths and 6 code rates of Quasi-Cyclic LDPC code for Mobile WiMAX system. To achieve an efficient implementation of 114 operation modes, some design optimizations are considered including block-serial layered decoding scheme, a memory reduction technique based on the min-sum decoding algorithm and a novel method for generating the cyclic shift values of parity check matrix. From fixed-point simulations, decoding performance and optimal hardware parameters are analyzed. The designed LDPC decoder is verified by FPGA implementation, and synthesized with a $0.18-{\mu}m$ CMOS cell library. It has 380,000 gates and 52,992 bits RAM, and the estimated throughput is about 164 ~ 222 Mbps at 56 MHz@1.8 V.

• Journal of Communications and Networks
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• v.13 no.5
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• pp.511-517
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• 2011

The capacity of wireless ad-hoc networks is analyzed for all kinds of information dissemination based on single and multiple packet reception schemes under the physical model. To represent the general information dissemination scheme, we use (n, m, k)-cast model [1] where n, m, and k (k ${\leq}$ m) are the number of nodes, destinations and closest destinations that actually receive packets from the source in each (n, m, k)-cast group, respectively. We first consider point-to-point communication, which implies single packet reception between transmitter-receiver pairs and compute the (n, m, k)-cast communications. Next, the achievable throughput capacity is computed when receiver nodes are endowed with multipacket reception (MPR) capability. We adopt maximum likelihood decoding (MLD) and successive interference cancellation as optimal and suboptimal decoding schemes for MPR. We also demonstrate that physical and protocol models for MPR render the same capacity when we utilize MLD for decoding.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.11
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• pp.1248-1255
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• 2012

LDPC decoder architectures are generally classified into serial, parallel and partially parallel architectures. Conventional method of LDPC decoding in general give rise to a large number of computation operations, mass power consumption, and decoding delay. It is necessary to reduce the iteration numbers and computation operations without performance degradation. This paper studies horizontal shuffle scheduling(HSS) algorithm and self-correction normalized min-sum(SC-NMS) algorithm. In the result, number of iteration is half than conventional algorithm and performance is almost same between sum-product(SP) and SC-NMS. Finally, This paper implements high-speed LDPC decoder based on FPGA. Decoding throughput is 816 Mbps.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.20-25
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• 2005

A high performance Viterbi decoder is designed using modified register exchange scheme and block decoding method. The elimination of the trace-back operation reduces the operation cycles to determine the merging state and the amount of memory. The Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoding methods in block decoding architectures. The elimination of trace-back also reduces the power consumption for finding the merging state and the access to the memory. The proposed decoder can be designed with emphasis on either efficient memory or low latency. Also, it has a scalable structure so that the complexity of the hardware and the throughput are adjusted by changing a few design parameters before synthesis.