• ETRI Journal
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• v.31 no.3
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• pp.336-338
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• 2009

This letter proposes a complexity reduction method to speed up the noiseless decoding of a bit-sliced arithmetic coding (BSAC) decoder. This scheme fully utilizes the group of consecutive arithmetic-coded symbols known as the decoding band and the significance tree structure sorted in order of significance at every decoding band. With the same audio quality, the proposed method reduces the number of calculations that are performed during the noiseless decoding in BSAC to about 22% of the amount of calculations with the conventional full-search method.

• Journal of Advanced Navigation Technology
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• v.15 no.3
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• pp.392-404
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• 2011

In this paper, we address the issue of joint detection schemes for uplink cellular system when base station cooperation is possible for multi-user detection in multi-cell scenario. The ZF, ML, MMSE and SIC detection are analyzed and evaluated as a conventional scheme. ML attains the optimal performance but the complexity increases exponentially, ZF/MMSE have simple structure but have poor detection performance and SIC has better performance but it has large complexity and potential of the error propagation. However, they need the increased decoder complexity as the number of iteration is increased. We propose a new joint ML and ZF/MMSE detection scheme, which combines the partial ML decoding and ZF/MMSE detection, in order to decrease the decoder complexity. Simulation results show that the proposed scheme attains same or a little bit better BER performance and expect reduced decoder complexity, specially in the case of large number of Base Station are cooperated each other.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2367-2372
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• 2015

One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12A
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• pp.1387-1395
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• 2004

Turbo decoder inherently requires large memory and intensive hardware complexity due to iterative decoding, despite of excellent decoding efficiency. To decrease the memory space and reduce hardware complexity, various design issues have to be discussed. In this paper, various design issues on Turbo decoder are investigated and the tradeoffs between the hardware complexity and the performance are analyzed. Through the various simulations on the fixed-length analysis, we decided 5-bits for the received data, 6-bits for a priori information, and 7-bits for the quantization state metric, so the performance gets close to that of infinite precision. The MAX operation which is the main function of Log-MAP decoding algorithm is analyzed and the error correction term for MAX* operation can be efficiently implemented with very small hardware overhead. The size of the sliding window was decided as 32 to reduce the state metric memory space and to achieve an acceptable BER.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.11
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• pp.78-89
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• 2013

This paper proposes a high-throughput and multi-mode quasi-cyclic (QC) low-density parity-check (LDPC) decoder based on a fully parallel structure. The proposed QC-LDPC decoder employs the fully parallel structure to provide very high throughput. The high interconnection complexity, which is the general problem in the fully parallel structure, is solved by using a broadcasting-based sum-product algorithm and proposing a low-complexity cyclic shift network. The high complexity problem, which is caused by using a large amount of check node processors and variable node processors, is solved by proposing a combined check and variable node processor (CCVP). The proposed QC-LDPC decoder can support the multi-mode decoding by proposing a routing-based interconnection network, the flexible CCVP and the flexible cyclic shift network. The proposed QC-LDPC decoder is operated at 100 MHz clock frequency. The proposed QC-LDPC decoder supports multi-mode decoding and provides 8.1 Gbps throughput for a (1944, 1620) QC-LDPC code.

• ETRI Journal
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• v.30 no.6
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• pp.807-817
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• 2008

We present a low-density parity-check (LDPC)-based, threaded layered space-time-frequency system with emphasis on the iterative receiver design. First, the unbiased minimum mean-squared-error iterative-tree-search (U-MMSE-ITS) detector, which is known to be one of the most efficient multi-input multi-output (MIMO) detectors available, is improved by augmentation of the partial-length paths and by the addition of one-bit complement sequences. Compared with the U-MMSE-ITS detector, the improved detector provides better detection performance with lower complexity. Furthermore, the improved detector is robust to arbitrary MIMO channels and to any antenna configurations. Second, based on the structure of the iterative receiver, we present a low-complexity belief-propagation (BP) decoding algorithm for LDPC-codes. This BP decoder not only has low computing complexity but also converges very fast (5 iterations is sufficient). With the efficient receiver employing the improved detector and the low-complexity BP decoder, the proposed system is a promising solution to high-data-rate transmission over selective-fading channels.

• Journal of the Institute of Electronics Engineers of Korea CI
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• v.42 no.3 s.303
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• pp.53-62
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• 2005

In the decoding process of interframe Wavelet coding, the Wavelet transform requires huge computational complexity. Since the decoder may need to be used in various devices such as PDAs, notebooks, or PC, the decoder's complexity should be adapted to the processor's computational power. So, it is natural that the low complexity codec is also required for scalable video coding. In this paper, we develop a method of controlling and lowering the complexity of the spatial Wavelet transform while sustaining the same coding efficiency as the conventional spatial Wavelet transform. In addition, the proposed method may alleviate the ringing effect for slowly changing image sequences.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.9 s.339
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• pp.73-80
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• 2005

The Turbo decoders based on Log-MAP decoding algorithm inherently requires large amount of memory and intensive complexity of hardware due to iterative decoding, despite of excellent decoding efficiency. To decrease the large amount of memory and reduce hardware complexity, the result of previous research. And this paper design the Turbo decoder applicable to the 3G W-CDMA systems. Through the result of previous research, we decided 5-bits for the received data 6-bits for a priori information, and 7-bits for the quantization state metrics. The error correction term for $MAX^{*}$ operation which is the main function of Log-MAP decoding algorithm is implemented with very small hardware overhead. The proposed Turbo decoder is synthesized in $0.35\mu$m Hynix CMOS technology. The synthesized result for the Turbo decoder shows that it supports a maximum 9Mbps data rate, and a BER of $10^{-6}$ is achieved(Eb/No=1.0dB, 5 iterations, and the interleaver size $\geq$ 2000).

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.20-25
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• 2005

A high performance Viterbi decoder is designed using modified register exchange scheme and block decoding method. The elimination of the trace-back operation reduces the operation cycles to determine the merging state and the amount of memory. The Viterbi decoder has low latency, efficient memory organization, and low hardware complexity compared with other Viterbi decoding methods in block decoding architectures. The elimination of trace-back also reduces the power consumption for finding the merging state and the access to the memory. The proposed decoder can be designed with emphasis on either efficient memory or low latency. Also, it has a scalable structure so that the complexity of the hardware and the throughput are adjusted by changing a few design parameters before synthesis.

• Proceedings of the IEEK Conference
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• 2004.06a
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• pp.265-268
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• 2004

In this paper. we propose an adaptive step-size algorithm for the adaptive interference canceller (AIC) in the space-time trellis coded DS-CDMA system. In the AIC, the performance of the blind LMS algorithms that updates the tap-weight vector of the AIC is heavily dependent on the choice of step-size. To improve the performance of the fixed step-size AIC (FS-AIC), the regular adaptive step-size algorithm is extended in complex domain and applied to the joint AIC and ML decoder scheme. Simulation results show that the joint adaptive step-size AIC (AS-AIC) and ML decoder scheme using the proposed algorithm has boner performance than not only the conventional ML decoder but also the joint FS-AIC and ML decoder scheme without much increase of the decoding delay and complexity.