• Journal of Broadcast Engineering
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• v.15 no.5
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• pp.642-652
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• 2010

Recently, DVC (Distributed Video Coding) techniques are drawing a lot of interests as one of the future research works to achieve low complexity encoding in various applications. But, due to the limited computational complexity, the performances of DVC algorithms are inferior to those of conventional international standard video coders, which use zig-zag scan, run length code, entropy code and skipped macroblock. In this paper, in order to overcome the performance limit of the DVC system, the distortion for every block is estimated when side information is found at the decoder and then we propose a new selective block encoding scheme which provides the encoder side with the motion information for the highly distorted blocks and then allows the sender to encode the motion compensated frame difference signal. Through computer simulations, it is shown that the coding efficiency of the proposed scheme reaches almost that of the conventional inter-frame coding scheme.

• The KIPS Transactions:PartC
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• v.11C no.1
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• pp.75-80
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• 2004

An iterative soft-decision decoding algorithm of block codes is proposed. With careful examinations of the first hard-decision decoding result, the candidate codewords are efficiently searched for. An approach to reducing decoding complexity and lowering error probability is to select a small number of candidate codewords. With high probability, we include the codewords which are at the short distance from the received signal. The decoder then computes the distance to each of the candidate codewords and selects the codeword which is the closest. We can search for the candidate codewords which make the error patterns contain the bits with small reliability values. Also, we can reduce the cases that we select the same candidate codeword already searched for. Computer simulation results are presented for (23,12) Golay code. They show that decoding complexity is considerably reduced and the block error probability is lowered.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.37 no.7A
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• pp.535-544
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• 2012

Multi-Input Multi-Output (MIMO) transmission is now considered as one of essential techniques enabling high rate data transmissions in wireless communication systems. In addition, severe channel impairments in wireless systems should be compensated by using highly efficient forward error correction (FEC) codes. Turbo codes or low density parity check (LDPC) codes, using iterative decoding with soft decision detection information (SDDI), are the most common examples. The excellent performance of these codes should be conditioned on accurate estimation of SDDI from the MIMO detection process. In this paper, we propose a soft MIMO detection scheme using QR decomposition of channel matrices as an efficient means to provide accurate SDDI to the iterative decoder. The proposed method employed a two sequential soft MIMO detection process in order to reduce computational complexity. Compared to the soft ZF method calculating the direct inverse of the channel matrix, the complexity of the proposed method can be further reduced as the number of antennas is increased, without any performance degradation.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.41 no.12
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• pp.1834-1843
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• 2016

DVRs are the most common recording and displaying devices used for surveillance. Video compression plays a key role in DVRs for saving storage; the video compression standard, H.264/AVC, has recently become the dominant choice for DVRs. DVRs require various display modes, such as fast-forward, backward play, and pause; these are called trick modes. The implementation of precise trick mode play requires a very high decoding capability or a very intelligent scheme in order to handle the high computation complexity. The complexity is increased in many surveillance applications where more than one camera is used to monitor multiple spots or to monitor the same area using various angles. An implementation of a trick mode play and a frame buffer management scheme for the hardware-based H.264/AVC codec for multi-channel is presented in this paper. The experimental results show that exact trick mode play is possible using a standard H.264/AVC video codec with keyframe encoding feature at the expense of bitstream size increase.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.45 no.2
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• pp.37-43
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• 2008

The performance and hardware complexity of LDPC decoders depend on the design parameters of quantization, the clipping threshold $c_{th}$ and the number of quantization bits q, and also on the maximum number of decoding iterations. In this paper, the BER performances of LDPC codes are evaluated according to the clipping threshold $c_{th}$ and the number of quantization bits q through the simulation studies. By comparing the quantized Min-Sum algorithm with the ideal Min-Sum algorithm, it is shown that the quantized case with $c_{th}=2.5$ and q=6 has the best performance, which approaches the idea case. The decoding complexities are calculated and the word error rates(WER) are estimated by using the pdf which is obtained through the statistical analyses on the iteration numbers. These results can be utilized to tradeoff between the decoding performance and the complexity in LDPC decoder design.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.5C
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• pp.295-301
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• 2011

In [1], it has been shown that the energy spreading transform (EST) based iterative equalizer (IE) could enhance its performance by improving the reliability of the decision feedback symbols without the help of the complicated channel decoder. In the matched filter (MF) based IE proposed in [1], however, its feedforward filter (FFF) has been designed in the frequency domain while its feedback filter (FBF) in the time domain. So its complexity increases proportional to the channel memory length. To solve this problem, in this paper, both FFF and FBF are designed in the frequency domain. This enables the proposed frequency domain IE (FD-IE) to achieve the lower complexity over the conventional method in the highly dispersive channel. In addition, simulation results demonstrate that the BER performance of the proposed method is the same as the conventional.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.4C
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• pp.191-199
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• 2005

Space-time turbo codes have been studied extensively as a powerful and bandwidth efficient error correction code over the wireless communication environment. In this paper, the efficient algorithm for decoding space-time turbo codes is proposed. The proposed method reduces the computational complexity by approximating a prior information for a iterative decoder. The performance of space-time turbo codes is also analyzed by using the fixed point implementation and the efficient method for approximating the Log-MAP algorithm is proposed. It is shown that the BER performance of the proposed method is close to that of the Log-MAP algorithm.

• Journal of KIISE:Computing Practices and Letters
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• v.6 no.4
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• pp.448-456
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• 2000

As the system complexity increases, it is important to develop high-level verification techniques for fast and efficient design verifications. In this research, fast verification techniques for hardware and software co-design systems have been developed by using logic emulation and algorithm-level simulation. For faster and superior functional verification, we partition the system being designed into hardware and software parts, and implement the divided parts by using interface modules. We also propose several hardware design techniques for efficient hardware emulation. Experimental results, obtained by using a Reed-Solomon decoder system, show that our new verification methodology is more than 12,000 times faster than a commercial simulation tool for the modified Euclid's algorithm block and the overall verification time is reduced by more than 50%.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.85-95
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• 2004

As the design complexity increases, it is a major problem that the size of test pattern is large and power consumption is high in scan, especially system-on-a-chip(SoC), with the automatic test equipment(ATE). Because static compaction of test patterns heads to higher power for testing, it is very hard to reduce the test pattern volume for low power testing. This paper proposes an efficient compression/decompression algorithm based on run-length coding for reducing the amount of test data for low power testing that must be stored on a tester and be transferred to SoC. The experimental results show that the new algorithm is very efficient by reducing the memory space for test patterns and the hardware overhead for the decoder.

• ETRI Journal
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• v.39 no.4
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• pp.582-591
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• 2017

To address the wire complexity problem in large-scale globally asynchronous, locally synchronous systems, a current-mode ternary encoding scheme was devised for a two-phase asynchronous protocol. However, for data transmission through a very long wire, few studies have been conducted on reducing the long propagation delay in current-mode circuits. Hence, this paper proposes a current steering logic (CSL) that is able to minimize the long delay for the devised current-mode ternary encoding scheme. The CSL creates pulse signals that charge or discharge the output signal in advance for a short period of time, and as a result, helps prevent a slack in the current signals. The encoder and decoder circuits employing the CSL are implemented using $0.25-{\mu}m$ CMOS technology. The results of an HSPICE simulation show that the normal and optimal mode operations of the CSL achieve a delay reduction of 11.8% and 28.1%, respectively, when compared to the original scheme for a 10-mm wire. They also reduce the power-delay product by 9.6% and 22.5%, respectively, at a data rate of 100 Mb/s for the same wire length.