• 제목/요약/키워드: Dead time control

검색결과 332건 처리시간 0.03초

Dead-Time 적응제어 기능과 Power Switching 기능을 갖는 DC-DC 부스트 변환기 (DC-DC Boost Converter with Dead-Time Adaptive Control and Power Switching)

  • 이주영;양민재;김두회;윤은정;유종근
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2013년도 추계학술대회
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    • pp.361-364
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    • 2013
  • 기존의 DC-DC 부스트 변환기에서 사용되는 non-overlapping gate driver는 dead-time이 고정되어 있기 때문에 body-diode conduction loss 또는 charge-sharing loss가 발생하는 문제점을 가지고 있다. 이러한 손실을 줄이기 위해 사용된 기존의 적응제어 방식의 경우는 CCM 동작 시 전력트랜지스터가 동시에 on이 되는 구간이 발생하여 시스템 효율이 감소하는 문제점이 있다. 따라서 본 논문 에서는 이러한 문제점을 해결할 dead-time 적응제어 기능과 power switching 기능을 갖는 DC-DC 부스트 변환기를 설계 하였다. CMOS 0.35um 공정을 사용하였고, 2.5V 입력으로 3.3V의 출력전압을 얻으며, 스위칭 주파수는 500kHz 이다. 부하전류 150mA일 때 가장 높은 95.3%의 효율을 얻었다. 설계된 회로의 칩 면적은 $1720um{\times}1280um$이다.

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Topology Generation and Analysis of the No Dead Time AC/DC Converter

  • Zheng, Xinxin;Xiao, Lan;Tian, Yangtian
    • Journal of Power Electronics
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    • 제14권2호
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    • pp.249-256
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    • 2014
  • A novel topology generation method for the no dead-time three-phase AC/DC converter is proposed in this study. With this method, a series of no dead time topologies are generated and their operation principles are analyzed. The classic three-phase bridge AC/DC converter can realize a bidirectional operation. However, dead-time should be inserted in the driving signals to avoid the shoot-through problem, which would cause additional harmonics. Compared with the bridge topology, the proposed topologies lack the shoot-through problem. Thus, dead time can be avoided. All of the no dead time three-phase AC/DC converters can realize bidirectional operation. The operating principles of the converters are analyzed in detail, and the corresponding control strategies are discussed. Comparisons of waveform distortion and efficiency among the converters are provided. Finally, 9 KW DSP-based principle prototypes are established and tested. Simulation and experimental results verify the theoretical analysis.

CHB 인버터 셀의 데드타임 구현 방법 (Dead-Time Implementation Method for CHB Inverter Cells)

  • 김경서
    • 전력전자학회논문지
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    • 제26권1호
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    • pp.59-65
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    • 2021
  • This study proposes a dead-time implementation method suitable for cell voltage control of a cascaded H-bridge (CHB) inverter. The PWM module of an existing microcontroller cannot generate a maximum voltage due to the dead-time effect when used as the cell controller of the CHB inverter. In the proposed method, the operation method of the PWM module was changed without using the dead time module included in the existing microcontroller, so that the cell output voltage can be increased to the maximum voltage without voltage discontinuity. During the maximum voltage generation period, the full turn-on state can be maintained without unnecessary switching. The validity of the proposed method is confirmed through an experiment.

영구자석 동기 전동기의 MRAS 관측기를 이용한 Dead Time 보상에 대한 연구 (Study on Dead Time Compensation using MRAS Observer of Permanent Magnet Synchronous Motor.)

  • 김종현;김학원;조관열;임병국
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 2013년도 추계학술대회 논문집
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    • pp.41-43
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    • 2013
  • PMSM 구동을 하였을 때, 인버터의 지령전압과 출력전압 사이에 왜곡이 발생하며, 대부분 Dead Time에 의한 영향 이다. 전압왜곡을 보상하는 여러 가지 방법 들이 연구되어왔다. 하지만 전압 왜곡의 보상이 abc 축 또는 dq축에서 이루어지고 있으나 어느 방식이 더 좋은지에 대한 검토가 없었다. 본 논문에서는 d-q축 전압방정식과 abc축 전압방정식으로부터 왜곡된 전압을 보상하는 방법을 비교한다.

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CMOS 0.18um 공정을 이용한 Dead-Time 적응제어 기능을 갖는 PWM DC-DC Boost 변환기 설계 (Design of a PWM DC-DC Boost Converter with Adaptive Dead-Time Control Using a CMOS 0.18um Process)

  • 황인호;윤은정;박종태;유종근
    • 한국정보통신학회:학술대회논문집
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    • 한국정보통신학회 2012년도 추계학술대회
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    • pp.285-288
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    • 2012
  • 기존의 DC-DC Boost 변환기에 사용되는 일반적인 non-overlapping gate driver는 dead-time이 고정되어 있기 때문에 body-diode conduction loss 또는 charge-sharing loss가 발생하는 문제점이 있다. 따라서 본 논문에서는 이러한 loss에 의한 효율 감소를 줄이기 위해 dead-time 적응제어 기능을 갖는 PWM DC-DC Boost 변환기를 설계하였다. 또한, 부하전류가 작은 경우 효율을 증가시키기 위해 power switching 회로를 사용하였다. 그 결과 넓은 부하 전류 범위에서 높은 효율을 얻을 수 있다. 제안된 DC-DC Boost 변환기는 CMOS 0.18um공정으로 설계하였다. 2.5V의 입력전압을 받아서 3.3V의 출력전압을 얻는다. 스위칭 주파수는 500kHz이며, 최대효율은 97.8%이다.

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Genetic Algorithm for Identification of Time Delay Systems from Step Responses

  • Shin, Gang-Wook;Song, Young-Joo;Lee, Tae-Bong;Choi, Hong-Kyoo
    • International Journal of Control, Automation, and Systems
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    • 제5권1호
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    • pp.79-85
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    • 2007
  • In this paper, a real-coded genetic algorithm is proposed for identification of time delay systems from step responses. FOPDT(First-Order Plus Dead-Time) and SOPDT(Second-Order Plus Dead-Time) systems, which are the most useful processes in this field, but are difficult for system identification because of a long dead-time problem and a model mismatch problem. Genetic algorithms have been successfully applied to a variety of complex optimization problems where other techniques have often failed. Thus, the modified crossover operator of a real-code genetic algorithm is proposed to effectively search the system parameters. The proposed method, using a real-coding genetic algorithm, shows better performance characteristics when compared to the usual area-based identification method and the directed identification method that uses step responses.

Design of Digital Controller for Uninterruptible Power Supply Using Disturbance Observer

  • Cho, Jun-Seok;Lee, Seung-Yo;Mok, Hyung-Soo;Choe, Gyu-Ha
    • 전력전자학회:학술대회논문집
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    • 전력전자학회 1998년도 Proceedings ICPE 98 1998 International Conference on Power Electronics
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    • pp.830-835
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    • 1998
  • This paper describes a new digital control method of 3-phase PWM inverter with LC filter for uninterruptible power supply(UPS). The overall control system is based on the dead beat control, which has the minor loop of current control within the voltage control major loop. In this paper, the full-order disturbance observer is proposed to compensate the disturbances generated due to a sudden change of load currents. The proposed disturbance observer is composed of dead beat observer which estimates state values within a finite time, and cancels the disturbances by adding feedforward compensation loop in the control system. In addition, on order to remove a defect of oscillation generated in output of conventional dead beat controller, a modified dead beat algorithm is proposed in this paper.

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Real-coded genetic algorithm for identification of time-delay process

  • Shin, Gang-Wook;Lee, Tae-Bong
    • 제어로봇시스템학회:학술대회논문집
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    • 제어로봇시스템학회 2005년도 ICCAS
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    • pp.1645-1650
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    • 2005
  • FOPDT(First-Order Plus Dead-Time) and SOPDT(Second-Order Plus Dead-Time) process, which are used as the most useful process in industry, are difficult about process identification because of the long dead-time problem and the model mismatch problem. Thus, the accuracy of process identification is the most important problem in FOPDT and SOPDT process control. In this paper, we proposed the real-coded genetic algorithm for identification of FOPDT and SOPDT processes. The proposed method using real-coding genetic algorithm shows better performance characteristic comparing with the existing an area-based identification method and a directed identification method that use step-test responses. The proposed strategy obtained useful result through a number of simulation examples.

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지연요소를 수반하는 일차계통의 패러미터 추정에 관한 연구 (A Study of Parameter Estimation for First Order System with Dead Time)

  • 하주식
    • 전기의세계
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    • 제18권1호
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    • pp.15-23
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    • 1969
  • A lot of recent researches have shown that a Pseudo Random Binary Signal is a quite effective test signal to measure the impulse response of a plant. Generally speaking, however, such a response itself is not satisfactory to determine the appropriate control parameters or control inputs. Here, the author intends to estimate the unknown parameters of the First Order Plant with Dead Time by means of correlation method using M-sequence signal. The time constant T and the dead time L of the plant are eatimated with one tracking loop by automatically adjusting delay time .tau. of M-sequence signal according to variations of T and L. In this paper, a three level M-sequence signal is used as a test signal in order to avoid troublesome operations to calculate partial derivatives of a given performance index with respect to the parameters which are usually required in the Model Method. Several experiments with analogue computer using low pass filters as averaging circuits showed good results as expected.

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브리지 형태 PWM 변환기의 데드타임 최소화 방법 (A New Dead Time Minimization Method for the Bridge Type PWM Converters)

  • 김남정;이을재;오원석;조규민
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 하계학술대회 논문집 F
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    • pp.2715-2720
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    • 1999
  • To prevent the short circuit of upper and lower arms of bridge type PWM converters as like a voltage source inverter and PWM AC/DC converter, the dead time is inserted in between two switching signals. As a result, unexpected errors are occurred. In this paper, a new dead time minimization method is proposed. According to the proposed method, very short time which is equal to the applied dead time or more short than it, is adopted at the time of current polarity is changing. Moreover, it can be operated with the polarity information of reference current in case of current control. With the experimental results. the varidity of proposed method is verified.

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