• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송공학회 1999년도 학술대회
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• pp.255-260
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• 1999

본 논문에서는 데이터 입출력을 고속으로 수행하며 작은 지연시간을 갖는 512-point FFT프로세서의 구조및 설계에 대하여 보인다. 설계된 512-point FFT프로세서는 OFDM방송에서 요구하는 심볼 레이트로 테이타를 처리할 수 있는 것을 목표로 하였다. 설계된 512-point FFT프로세서는 써플메모리를 이용하여 메모리의 요구사항을 최소화하며, 새로운 strength reduction method를 적용한 복소곱셈기를 이용하여 기존의 복소곱셈기에 비하여 하드웨어의 비용이 적은 특징을 갖는다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 1992년도 한국자동제어학술회의논문집(국내학술편); KOEX, Seoul; 19-21 Oct. 1992
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• pp.61-66
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• 1992

In this paper, a method for implementing software for the control system with dual structure in processor module is proposed and implemented to enhance its reliability. In this implementation the multi-tasking function which is provided by a real-time operating system is applied. The overall softwre is divided into five tasks and is performed in each of the dual processor module, independently. By this, the processor module with dual structure can achieve a control objective and fault diagnostics effectively. An experimental result shows that the backup processor module can be substituted for the primary processor module immediately when it happens to fail, because data relating the failure information are exchanged continuously done via shared memories.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2006년도 하계종합학술대회
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• pp.533-534
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• 2006

This paper presents the architecture design of a high-speed, low-complexity 128-point radix-$2^4$ FFT processor for ultra-wideband (UWB) systems. The proposed high-speed, low-complexity FFT architecture can provide a higher throughput rate and low hardware complexity by using 2-parallel data-path scheme and single-path delay-feedback (SDF) structure. This paper presents the key ideas applied to the design of high-speed, low-complexity FFT processor, especially that for achieving high throughput rate and reducing hardware complexity. The proposed FFT processor has been designed and implemented with the 0.18-m CMOS technology in a supply voltage of 1.8 V. The throughput rate of proposed FFT processor is up to 1 Gsample/s while it requires much smaller hardware complexity.

• 전자공학회논문지B
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• 제30B권7호
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• pp.1-13
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• 1993

In this paper, the problems of the conventional special-purpose array processor such as the deficiency of flexibility have been investigated. Then, a new modified methodology has been suggested and applied to obtain the common solution of the three typical App algorithms like SP(Shortest Path), TC(Transitive Closure), and MST(Minimun Spanning Tree) among the various APP algorithms using the similar method to obtain the solution. In the newly proposed APP parallel algorithm, real-time Processing is possible, without the structure enhancement and the functional restriction. In addition, we design 2-demensional bit-parallel low-triangular systolic array processor and the 1-PE in detail. For its evaluation, we consider its computational complexity according to bit-processing method and describe relationship of total chip size and execution time. Therefore, the proposed processor obtains, on which a large data inputs in real-time, 3n-4 execution time which is optimal o(n) time complexity, o(n$^{2}$) space complexity which is the number of total gate and pipeline period rate is one.

• 한국철도학회논문집
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• 제5권2호
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• pp.55-60
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• 2002

This study proposes the post-processor simulator construction of ultrasonic signal for integrity evaluation of railway truck. For these purposes, the ultrasonic signals for defects(crack) of weld zone in frames are acquired in the type of time series data and echo strength. The detection of the natural defects in railway truck is performed using the characteristics of echodynamic pattern in ultrasonic signal. The constructed post-processor simulator agree fairly well with the measured results of test block(defect location, beam propagation distance, echo strength, etc). Proposed post-processor simulator construction of ultrasonic in this study can be used for the integrity evaluation of railway truck.

• 대한임베디드공학회논문지
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• 제6권2호
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• pp.100-107
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• 2011

As the use of mobile multimedia devices is increasing in the recent year, the needs for high-performance multimedia processors are increasing. In this regard, we propose a SIMD (Single Instruction Multiple Data) based parallel processor that supports high-performance multimedia applications with low energy consumption. The proposed parallel processor consists of 16 processing elements(PEs) and operates on a 3-stage pipelining. Experimental results for the JPEG encoding algorithm indicate that the proposed parallel processor outperforms conventional parallel processors in terms of performance and energy efficiency. In addition, the proposed parallel processor architecture was developed and verified with verilog HDL and a FPGA prototype system.

• 한국정보통신학회:학술대회논문집
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• 한국정보통신학회 2012년도 춘계학술대회
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• pp.504-505
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• 2012

본 논문에서는 효율적인 멀티미디어 프로세서에 대해 논의하였으며 그 응용으로 디지털 워터마킹에 적용하였다. 즉, 인간의 시각이나 청각이 인지할 수 없는 범위 내에서 디지털 데이터의 값을 약간 변경함에 따라 워터마크라고 하는 저작권 정보를 몰래 삽입하는 방법이다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.603-604
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• 2008

This paper implemented The LED illuminance control IP based on 8bit RISC Processor. 8bit RISC Processor designed hardware interrupts, an interface for serial communications, a timer system with compare-capture-reload resources and a watchdog timer. LED Array consists of Red, Green, Blue, White and Warm White. The illuminance control IP is used to LED Board control with 8bit data.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.97-100
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• 2001

A 3-way VLIW multimedia signal processor capable of efficient repeated operations as well as both load/store and type transformations for various data types is presented. It is composed of a 32-bit execution unit that can execute two instructions in parallel, an independent load/store unit and a control unit. The processor is implemented with 0.6${\mu}{\textrm}{m}$ gate array and the results are discussed.

• 대한원격탐사학회지
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• 제21권5호
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• pp.371-382
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• 2005

We present a processing system for the Atmospheric Infrared Sounder (AIRS) sounding suite onboard Aqua satellite. With its unprecedented 2378 channels in IR bands, AIRS aims at achieving the sounding accuracy of radiosonde (1 K in 1-km layer for temperature and $10\%$ in 2-km layer for humidity). The core of the processor is the International MODIS/AIRS Processing Package (IMAPP) that performs the geometric and radiometric correction for generation of Level 1 brightness temperature and Level 2 geophysical parameters retrieval. The processor can produce automatically from received raw data to Level 2 geophysical parameters. As we process the direct-broadcast data almost for the first time among the AIRS direct-broadcast community, a special attention is paid to understand and verify the Level 2 products. This processor includes sub-systems, that is, the near real time validation system which made the comparison results with in-situ measurement data, and standard digital information system which carry out the data format conversion into GRIdded Binary II (GRIB II) standard format to promote active data communication between meteorological societies. This processing system is planned to encourage the application of geophysical parameters observed by AIRS to research the aqua cycle in the Korean peninsula.