• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.8B
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• pp.1586-1592
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• 1999

In DWMT, CMFB is employed in the synthesis/analysis part. The CMFB uses filters of greater length than the DFT, resulting in reduced interference between the carriers. In addition, the CMFB system is computationally efficient and fast algorithms are available for their implementation. Traditional designs for the prototype filters of CMFB usually involve nonlinear optimizations. Thus the required design time is considerably large even for small filter orders. In this paper, a prototype filter design method for CMFB is presented using optimal window method. The design process is reduced to the optimization of a single parameter and consequently the required design time is much less than those of the existing methods. It is shown that the stopband performance of the proposed method is better than that of the Kaiser window method.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.2
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• pp.126-131
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• 2004

Full search algorithm(FA) provides the best performance but this is usually impractical because of the large number of computations required for large search region. Fast search and conventional Boolean matching algorithms reduce computational complexity and data processing time but this algorithms have disadvantages that is difficult of implementation of hardware because of high control overhead and that is less performance than FA. This paper presents new Boolean matching algorithm, called BCBM(Bit Converted Boolean Matching). Proposed algorithm has performance closed to the FA by Boolean only block matching that may be very efficiently implemented in hardware for real time video communication. Simulation results show that the PSNR of the proposed algorithm is about 0.08㏈ loss than FA but is about 0.96∼2.02㏈ gain than fast search algorithm and conventional Boolean matching algorithm.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1689-1690
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• 2006

This study is for implementation of PC based Motor fault diagnosis system. By using harmonics and current signals of the motor, this system diagnoses the motor condition by accumulated harmonic contribution rate. In this proposed system that was composed of 5 parts. A sensor, connection box, evaluation board, device server, and main computer are those. There were two types of sensor, one was harmonic sensor the other was current sensors. The signal was acquired by sensor, and transferred to evaluation board. Second one is connection box. Because the output type of sensor and input type of evaluation board is different, connection box was necessary. Third one was evaluation board. The signal from the sensor was converted to digital signal in evaluation board. And this signal was transferred to device server. Fourth one was device server Device server transferred the data from evaluation board to main computer. And the last one was other parts controlled by main computer. In main computer, there were communication and diagnosis algorithms. The result was derived by main computer. In the result, there were 12 categories and 5 levels of motor conditions. The proposed system had some advantages comparing with stand alone type commercial motor fault diagnosis system. The first, by using remote access it was easier to get the conditions of motor. The second, there was no need to handle the sensors when users measured the motor signals. By this property, no one was necessary at motor location site. The third, this system was less restricted by times and places than commercial stand alone type diagnosis system. Therefore users can operate this system only using the main computer. Once the sensors are installed at the motor, users doesn't need to move to check up the condition of motors. Moreover, if there is ethernet hub, many motors can be not only diagnosed at once but also decreased its cost.

• The Journal of the Korea Contents Association
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• v.17 no.9
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• pp.281-291
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• 2017

Emotional interaction in virtual reality is necessary of social communication. However, social emotion has been tried to be less recognized quantitatively. This study was to determined social gaze of emotion in business domain. 417 emotion words were collected and 16 emotion words were selected to Goodness of Fit. Emotion word were mapped into 2 dimensional space through multidimensional scaling analysis. Then, X axis defined dimensions of cooperation, competition, and Y axis of low focus and high focus through the FGD. 52 subjects were presented to stimuli for emotion and gaze movement data were collected. Independent t-test results showed that the gaze factor increased in the face, eye, and nose areas at cooperation, and the gaze factor increased in the right face and nose areas at the low focus. It is expected that this will be used as a basic research to evaluate emotions needed in business environment in virtual space.

• Korean Institute of Interior Design Journal
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• v.18 no.6
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• pp.202-210
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• 2009

This research was undertaken to prove the relationship between street mall activation and architectural plan design. The research methodology was established based on the analysis of data of two existing street malls in Korea (Western Dome & LaFesta) and theoretical studies of outdoor space design. The findings from this study are the following: First, building blocks with segments in every 50m or so are ideal for detailed communication between visitors and building contents. Second, the ratio of width of main corridor and building height should be less than 1 to provide intimate feel and keep visitors' attention concentrated in the facility. Third, store unit should have more storefronts to be exposed more to passers-by and lead more pedestrian traffic. Fourth, shape of store unit would rather be wide and shallow, instead of narrow and deep, to have more exposure to the central corridor. Fifth, the building block of the busiest(most expensive) area that is usually at the main entrance area of street mall should be flexible to fit more smaller units to maximize the profitability. Sixth, the main entrance of store should face the main pedestrian corridor to induce the influx of visitors. Lastly seventh, anchor tenant that has strong name recognition is usually located on basement or higher level to induce pedestrian traffic into the mall, key tenants that are strong and familiar brand names should be located at the corner of building block with spacing to attract visitors, provide even distribution of traffic, and support wayfinding, and local tenant should be located at small units along the central corridor or remainder spaces occurred from building core layout.

• 한국정보통신설비학회:학술대회논문집
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• 2008.08a
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• pp.469-472
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• 2008

In this paper, we discuss the recent trends on the passive UHF RFID tag chip design techniques and several important system parameters. We also summarize link budget studies on both conventional and modem UHF RFID communications. The paper highlights the reverse link limited case, which has known to be the minor concern if reader continuous wave (CW) can reach the tag in sufficient level. This makes sense when the tag sensitivity is rather high (over 10-12${\mu}W$); however, since the tag chip fabrication technologies have been developed by time, the tag chip threshold levels are now less-dominant in determining link margin. If the tag limitation can be alleviated, the forward link limited case can be resolved; thus, we rather focus on the path-loss problem. Since the path-losses are still exist in both forward and reverse links, and it can be doubled while CW travels the reader-tag-reader path because forward link and reverse link are on the same distance. Consider if reader receiver sensitivity is very high in the worst case. In this case, weaken tag response (i.e., backscatters) cannot reach the level that reader receiver can process tag data; bit-error rate can be higher. Overall, backscatter levels should be high enough so that reader receiver can correctly function. After discussing link budget, we carried out practical measurements on fading effects between two circularly polarized UHF RFID antennas in a small scale area.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.3
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• pp.577-585
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• 2004

System Packet Interface Level 4 Phase(SPI-4.2) is an interface for packet and cell transfer between a physical layer(PHY) device and a link layer device, for aggregate bandwidths of OC-192 ATM and Packet Over Sonet/SDH(POS), as well as 10Gbps Ethernet applications. In this paper, we performs the research for SPI-4.2. Also we analyze the performance of SPI-4.2 interface module after modeling using C programming language. This paper shows that SPI-4.2 interface module with 512-word FIFO depth is able to be adapted for the offered loads to 97％ in random uniform traffic and 94％ in bursty traffic with bursty length 32. SPI-4.2 interface module can experience an performance degradation due to heavy overhead when it massively receives small size packets less than 14-byte. SPI-4.2 interface module is suited for line cards in gigabit/terabit routers, and optical cross-connect switches, and SONET/SDH-based transmission systems.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.10
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• pp.2375-2381
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• 2014

In case the coefficient set of an FIR filter is represented in the canonic signed digit (CSD) format with a few nonzero digits, it is possible to implement high data rate digital filters with low hardware cost. Designing an FIR filter with CSD format coefficients, whose number of nonzero signed digits is minimal, is equivalent to finding sparse nonzero signed digits in the coefficient set of the filter which satisfies the target frequency response with minimal maximum error. In this paper, a compressive sensing based CSD coefficient FIR filter design algorithm is proposed for multiplierless and high speed implementation. Design examples show that multiplierless FIR filters can be designed using less than two additions per tap on average with approximate frequency response to the target, which are suitable for high speed filtering applications.

• Journal of Biomedical Engineering Research
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• v.17 no.4
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• pp.449-458
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• 1996

Most of the conventional electrocardiowaphs foil to detect signals other than P-QRS-T due to the limited SNR and bandwidth. High-resolution electrocardiography(HRECG) provides better SNR and wider bandwidth for the detection of micro-potentials with higher frequency components such as vontricular late potentials(LP). We have developed a HRECG using uncorrected XYZ lead for the detection of LPs. The overall gain of the amplifier is 4000 and the bandwidth is 0.5-300Hz without using 60Hz notch filter. Three 16-bit A/D converters sample X, Y, and Z signals simultaneously with a sampling frequency of 2000Hz. Sampled data are transmitted to a PC via a DMA-controlled, optically-coupled serial communication channel. In order to further reduce the noise, we implemented a signal averaging algorithm that averaged many instances of aligned beats. The beat alignment was carried out through the use of a template matching technique that finds a location maximizing cross-correlation with a given beat tem- plate. Beat alignment error was reduced to $\pm$0.25ms. FIR high-pass filter with cut-off frequency of 40Hz was applied to remove the low frequency components of the averaged X, Y, and Z signals. QRS onset and end point were determined from the vector magnitude of the sigrlaIL and some parameters needed to detect the existence of LP were estimated. The entire system was designed for the easy application of the future research topics including the optimal lead system, filter design, new parameter extraction, etc. In the developed HRECG, without signal averaging, the noise level was less than 5$\mu$V$_rms RTI$. With signal averaging of at least 100 beats, the noise level was reduced to 0.5$\mu$V$_rms RTI$, which is low enough to detect LPs. The developed HRECG will provide a new advanced functionality to interpretive ECG analyzers.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.4
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• pp.691-698
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• 2008

This paper describes a 3.3V 10 bit CMOS digital-to-analog converter with a divided architecture of a 7 MSB and a 3 LSB, which uses an optimal Thermal-to-Binary Decoding method with monotonicity, glitch energy. The output stage utilizes here implements a return-to-zero circuit to obtain the dynamic performance. Most of D/A converters in decoding circuit is complicated, occupies a large chip area. For these problems, this paper describes a D/A converter using an optimal Thermal-to-Binary Decoding method. the designed D/A converter using the CMOS n-well $0.35{\mu}m$ process0. The experimental data shows that the rise/fall time, settling time, and INL/DNL are 1.90ns/2.0ns, 12.79ns, and a less than ${\pm}2.5/{\pm}0.7\;LSB$, respectively. The power dissipation of the D/A converter with a single power supply of 3.3V is about 250mW.