• 한국콘텐츠학회논문지
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• 제3권3호
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• pp.47-54
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• 2003

본 논문에서는 홍채인식 상용제품에 적용하기 위한 임베디드 시스템의 운영체제로서 리눅스를 대상으로 하여 홍채인식 시스템을 위한 UI 보드를 개발하교 구현된 보드에 리눅스를 포팅v하였다. 이를 위하여 구현된 UI 보드에 맞게 UNUX(전체시스템을 설계하고 부트로더, 커널, 제어 프로그램 등을 이에 맞도록 정합시켰다. 실험 결과, 홍채인식시스템은 정상적으로 동작하교 TCP/IP로 연결된 UI 보드는 타 시스템과 성공적으로 데이터를 실시간 송$.$수신함으로써 제품의 전체 기능상 신뢰성 있는 사용자 인터페이스 기능을 구현할 수 있었다.

• 한국멀티미디어학회논문지
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• 제14권10호
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• pp.1275-1286
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• 2011

This paper proposes a high speed systolic array architecture for full search block matching algorithm (FBMA). The pixels of the search area for a reference block are input only one time to find the matched candidate block and reused to compute the sum of absolute difference (SAD) for the adjacent candidate blocks. Each row of designed 2-dimensional systolic array compares the reference block with the adjacent blocks of the same row in search area. The lower rows of the designed array get the pixels from the upper row and compute the SAD with reusing the overlapped pixels of the candidate blocks within same column of the search area. This designed array has no data broadcasting and global paths. The comparison with existing architectures shows that this array is superior in terms of throughput through it requires a little more hardware.

• KIEAE Journal
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• 제10권4호
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• pp.123-130
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• 2010

A lot of construction companies in overseas markets of construction try to change 2D CAD to 3D CAD for improving business ability and change to Building Information Modeling(BIM) for integrating information produced from construction life cycle. In America, GSA(General Service Administration) requires a design drawing planed by BIM and in Singapore and Europe, the government encourages architectures to use this tool. Recently in the domestic market, many organizations related construction industry are aware of importance of 3D CAD integrated information, and try to use BIM. Therefore, this research would analyze how does BIM affect construction industry and derive influence factors and provide basic data for using BIM.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2000년도 추계학술대회 논문집 학회본부 D
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• pp.800-802
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• 2000

In this paper, we propose the Self-Organizing Networks(SON) based on competitive Fuzzy Polynomial Neuron(FPN) for the optimal design of nonlinear process system. The SON architectures consist of layers with activation nodes based on fuzzy inference rules. Here each activation node is presented as FPN which includes either the simplified or regression Polynomial fuzzy inference rules. The proposed SON is a network resulting from the fusion of the Polynomial Neural Networks(PNN) and a fuzzy inference system. The conclusion part of the rules, especially the regression polynomial uses several types of high-order polynomials such as liner, quadratic and modified quadratic. As the premise part of the rules, both triangular and Gaussian-like membership functions are studied. Chaotic time series data used to evaluate the performance of our proposed model.

• 전자공학회논문지B
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• 제32B권1호
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• pp.96-102
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• 1995

This paper presents the VHSIC Hardware Description Language(VHDL) implementation of the Fixed Point Covariance Lattice(FLAT) algorithm for an Linear Predictive Coding(LPC) analysis and its related algorithms, such as the forth order high pass Infinite Impulse Response(IIR) filter, covariance matrix calculation, and Spectral Smoothing Technique(SST) in the Vector Sum Exited Linear Predictive(VSELP) speech coder that has been Selected as the standard speech coder for the North America and Japanese digital cellular. Existing Digital Signal Processor(DSP) chips used in digital cellular phones are derived from general purpose DSP chips, and thus, these DSP chips may not be optimal and effective architectures are to be designed for the above mentioned algorithms. Then we implemented the VHDL code based on the C code, Finally, we verified that VHDL results are the same as C code results for real speech data. The implemented VHDL code can be used for performing logic synthesis and for designing an LPC Application Specific Integrated Circuit(ASOC) chip and DsP chips. We first developed the C language code to investigate the correctness of algorithms and to compare C code results with VHDL code results block by block.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.405-406
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• 2008

This paper presents a high performance 2D PE architecture for H.264 Motion Estimation(ME). While existing 2D PE architectures reuse the overlapped data of adjacent search windows scanned in 1 or 3-way, the new architecture scan adjacent windows and multiple paths instead of single raster and zigzag scanning of adjacent windows in 4 way(up,down,left,right). By reducing the redundant access factor by 1.4, the new 4-way search window improve the memory bandwidth by 70-58% compared with 1/3-way search window. With Altera Stratix-III implementation, the high performance 2D PE architecture deals with SD ($720{\times}480$) video of 2 reference frame, $48{\times}48$ search area and $16{\times}16$ macroblock by 30fps at 97.1MHz.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.152.4-152
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• 2001

We investigate, in this paper, the use of FPGA(Field Programmable Gate Array) architectures for real-time processing of digital linescan camera. The use of FPGAS for low-level processing represents an excellent tradeoff between software and special purpose hardware implementations. A library of modules that implement common low-level machine vision operations is presented. These modules are designed with gate-level hardware components that are compiled into the functionality of the FPGA chips. This new synchronous unidirectional interface establishes a protocol for the transfer of image and result data between modules. This reduces the design complexity and allows several different low-level operations to be applied to the same input image ...

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1308-1311
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• 2002

We present a low-power MPEG-4 video codec chip capable of delivering high-quality video data in wireless multimedia applications. The discussion will focus on the architectural design techniques for implementing a high-performance video compression/decompression chip at low power architectures. The proposed MPEG-4 video codec can perform 30 frames/s of QCIF or 7.5 frame/s of CIF at 27MHz for 128k∼144kbps. By introducing the efficiently optimized Frame Memory Interface architecture, low power motion estimation and embedded ARM microprocessor and AMBA interface, the proposed MPEG-4 video codec has low power consumption for wireless multimedia applications such as IMT-2000.

• 전자공학회논문지A
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• 제33A권5호
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• pp.155-164
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• 1996

The architecture of a programmable video codec IC is described that employs multiple vector processors in a single chip. The vector processors operate in parallel and communicate with one another through on-chip shared memories. A single scalar control processor schedules each vector processor independently to achieve real-tiem video coding with special vector instructions. With programmable interconnection buses, the proposed architecture performs multi-processing of tasks and data in video coding. Therefore, it can provide good parallelism as well as good programmability. especially, it can operate multithread video coding, which processes several independent image sequences simultaneously. We explain its scheduling, multithred video coding, and vector processor architectures. We implemented a prototype video codec with a 0.8um CMOS cell-based technology for the multi-standard videophone. This codec can execute video encoding and decoding simultaneously for the QCIF image at a frame rate of 30Hz.

• JSTS:Journal of Semiconductor Technology and Science
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• 제13권5호
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• pp.415-422
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• 2013

In this paper, we present Self-Checking look-up-table (LUT) based on Scalable Error Detection Coding (SEDC) scheme for use in fault-tolerant reconfigurable architectures. SEDC scheme has shorter latency than any other existing coding schemes for all unidirectional error detection and the LUT execution time remains unaffected with self-checking capabilities. SEDC scheme partitions the contents of LUT into combinations of 1-, 2-, 3- and 4-bit segments and generates corresponding check codes in parallel. We show that the proposed LUT with SEDC performs better than LUT with traditional Berger as well as Partitioned Berger Coding schemes. For 32-bit data, LUT with SEDC takes 39% less area and 6.6 times faster for self-checking than LUT with traditional Berger Coding scheme.