• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2015.07a
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• pp.489-490
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• 2015

객체의 인식을 위한 컴퓨터 비전 알고리즘은 안개와 비와 같은 기상이 좋지 않은 상황에서는 인식 성능이 떨어지고 있다. 이로 인하여 최근 악천후 환경에서 촬영된 영상으로부터 날씨 현상을 제거하는 기법들이 연구되고 있다. 빗줄기는 시공간적 무작위성으로 인하여 검출 및 제거가 어려운 현상이다. 또한 기존의 빗줄기 검출 및 제거 기법들은 대부분 고정된 카메라로부터 촬영된 영상을 대상으로 처리함으로써 자동차와 같은 움직임이 있는 촬영환경에서는 부적합하다. 최근에는 카메라나 객체의 움직임에 대응할 수 있는 빗줄기 검출 및 제거 알고리즘이 개발되고 있으나, 방대한 연산량이 필요하기 때문에 실시간이 불가능하다. 본 논문에서는 최근 연구되고 있는 카메라 움직임이 있는 환경에서 빗줄기 검출 및 제거 알고리즘을 DSP 환경에서 구현하고 내부 메모리 최적화와 EMDA 이용, 소프트웨어 파이프라인 등을 통해 최적화를 수행하여 실시간성을 보인다.

• Journal of Ubiquitous Convergence Technology
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• v.2 no.1
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• pp.12-17
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• 2008

In this paper, the 128bit AES block cipher algorithm OCB (Offset Code Book) mode for privacy and authenticity of high speed packet data was efficiently designed in C language level and was optimized to support the required capacity of contents server using high performance DSP. It is known that OCB mode is about two times faster than CBC-MAC mode. As an experimental result, the encryption / decryption speed of the implemented block cipher was 308Mbps, 311 Mbps respectively at 1GHz clock speed, which is 50% faster than a general design with 3.5% more memory usage.

• Journal of Broadcast Engineering
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• v.16 no.6
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• pp.1018-1025
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• 2011

Scalable Video Coding (SVC) extension of H.264/AVC is a new video coding standard for media convergence by providing diverse videos of different spatial-temporal-quality layers with a single bitstream. Recently, real-time SVC codecs are being developed for the application areas of surveillance video and mobile video, etc. This paper presents the design and implementation of a H.264/SVC decoder based on an embedded DSP using Open SVC Decoder (OSD) which is a real-time software decoder designed for the PC environment. The implementation consists of porting C code of the OSD software from PC to DSP environment, profiling the complexity performance of OSD with further optimization, and integrating the optimized decoder into the TI Davinci EVM (Evaluation Module). 50 QCIF/CIF frames or 15 SD frames per second can be decoded with the implemented DSP-based SVC decoder.

• The Journal of the Korea Contents Association
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• v.8 no.5
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• pp.72-81
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• 2008

High Performance DSP usually supports cache and internal memory. For an optimal implementation of a multimedia stream application on such a high performance DSP, one needs to utilize the cache and internal memory efficiently. In this paper, we investigate performance analysis of cache, and internal memory configuration and placement necessary to achieve an optimal implementation of multimedia stream applications like motion picture encoder on high performance DSP, TMS320C6000 series, and propose strategies to improve performance for cache and internal memory placement. From the results of analysis and experiments, it is verified that 2-way L2 cache configuration with the remaining memory configured as internal memory shows relatively good performance. Also, it is shown that L1P cache hit rate is enhanced when frequently called routines and routines having caller-callee relationships with them are continuously placed in the internal memory and that L1D cache hit rate is enhanced by the simple change of the data size. The results in the paper are expected to contribute to the optimal implementation of multimedia stream applications on high performance DSPs.

• Proceedings of the IEEK Conference
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• 2006.06a
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• pp.257-258
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• 2006

In this paper, we address several issues in the real time implementation of MPEG-1 Layer II decoder on a fixed-point digital signal processor (DSP), especially TMS320C6416. There is a trade-off between processing speed and the size of program/data memory for the optimal implementation. In a view of the speed optimization, we first convert the floating point operations into fixed point ones with little degradation in audio quality, and then the look-up tables used for the inverse quantization of the audio codec are forced to be located into the internal memory of the DSP. And then, window functions and filter coefficients in the decoder are precalculated and stored as constant, which makes the decoder faster even larger memory size is required. It is shown from the real-time experiments that the fixed-point implementation enables us to make the decoder with a sampling rate of 48 kHz operate with 3 times faster than real-time on TMS320C6416 at a clock rate of 600 MHz.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2008.05a
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• pp.734-737
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• 2008

This paper presents a new automatic TFT-LCD image quality optimization system. We also have developed new algorithms using 6-point programmable matching technique with reference gamma curve, and automatic power setting sequence. It optimizes automatically gamma adjustment and power setting registers in mobile TFT-LCD driver IC to reduce gamma correction error, adjusting time, and flicker. Developed algorithms and programs are generally applicable for most of the TFT-LCD modules. The proposed optimization system contains module-under-test (MUT, TFT-LCD module), control program, multimedia display tester for measuring luminance and flicker, and control board for interface between PC and TFT-LCD module. The control board is designed with DSP, and it supports various interfaces such as RGB and CPU. Developed automatic image quality optimization system showed significantly reduced gamma adjusting time, reduced flicker, and much less average gamma error than competing system. We believe that the proposed system is very useful to provide high image quality TFT-LCD and to reduce developing process time using optimized gamma-curve setting and automatic power setting.

• ETRI Journal
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• v.42 no.1
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• pp.54-66
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• 2020

Nowadays, the broad availability of cameras and embedded systems makes the application of computer vision very promising as a supporting technology for intelligent transportation systems, particularly in the field of vehicle tracking. Although there are several existing trackers, the limitation of using low-cost cameras, besides the relatively low processing power in embedded systems, makes most of these trackers useless. For the tracker to work under those conditions, the video frame rate must be reduced to decrease the burden on computation. However, doing this will make the vehicle seem to move faster on the observer's side. This phenomenon is called the fast motion challenge. This paper proposes a tracker called dynamic swarm particle (DSP), which solves the challenge. The term particle refers to the particle filter, while the term swarm refers to particle swarm optimization (PSO). The fundamental concept of our method is to exploit the continuity of vehicle dynamic motions by creating dynamic models based on PSO. Based on the experiments, DSP achieves a precision of 0.896 and success rate of 0.755. These results are better than those obtained by several other benchmark trackers.

• The Journal of the Acoustical Society of Korea
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• v.24 no.1
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• pp.52-57
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• 2005

The adaptive multirate wideband (AMR-WB) speech coder has an extended audio bandwidth from 50 Hz to 7 kBz and operates on nine speech coding bit-rates from 6.6 to 23.85 kbit/s. In this Paper, we present the real-time implementation of AMR-WB speech coder using 16bit fixed-point TMS320C5509 that has dual MAC units. Firstly, We implemented AMR-WB speech coder in C 1anguage level using intrinsics, and then performed optimization in assembly language. The computational complexity of the implemented AMR-WB coder at 23.85 kbit/s is 42.9 Mclocks. And this coder needs the program memory of 15.1 kwords, data ROM of 9.2 kwords and data RAM of 13.9 kwords.

• JSTS:Journal of Semiconductor Technology and Science
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• v.6 no.4
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• pp.234-239
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• 2006

In the past decade, several tools have been developed to automate the floating-point to fixed-point conversion for DSP systems. In the conversion process, a number of scaling shifts are introduced, and they inevitably alter the original code sequence. Recently, we have observed that a compiler can often be adversely affected by this alteration, and consequently fails to generate efficient machine code for its target processor. In this paper, we present an optimization technique that safely migrates scaling shifts to other places within the code so that the compiler can produce better-quality code. We consider our technique to be safe in that it does not introduce new overflows, yet preserving the original SQNR. The experiments on a commercial fixed-point DSP processor exhibit that our technique is effective enough to achieve tangible improvement on code size and speed for a set of benchmarks.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2014.06a
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• pp.160-162
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• 2014

A programmable video decoding system with multi-core DSP and co-processors is presented. This system is adopted by Digital TV SoC (System on Chip) and is used for FHD HEVC (High Efficiency Video Coding) decoder. Using the DSP based programmable solution, we can reduce commercialization period by one year because we can parallelize algorithm development, software optimization and hardware design. In addition to the HEVC decoding, the proposed system can be used for other application such as other video decoding standard for multi-format decoder or video quality enhancement.