• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1090-1091
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• 2007

전자빔은 전자석의 자기장에 의하여 궤도가 편향 또는 집속된다. 이 전자석에 사용되는 전원장치는 사용되는 부품들의 품질과 관련되는 제어 기술의 발전으로 성능이 크게 향상되고 있다. 이 논문에서는 DSP를 이용하여 IGBT를 구동하는데 있어 phase-shifting 기법을 적용한 병렬 운전으로 출력 특성이 크게 개선된 전원장치에 대하여 설명하였다. 이 장치의 기본사양은 ${\pm}\;350\;A$, 2.5 Hz 계단형태의 출력전류를 전자석에 제공하는 것이다. 출력전류 피드백과 입력전압 피드-포워드 제어구조를 적용하여 출력전류의 안정도를 개선하였다. 모의실험과 실제 전자석 구동실험을 통하여 개발된 전원장치가 다양한 용도에 편리하게 적용될 수 있음을 보여준다.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.12C
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• pp.1617-1622
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• 2004

MPEG/Audio decoder for mobile multimedia systems requires low power consumption. Implementations of AV decoder using a single RISC processor often need high power consumption owing to cash-miss in case of insufficient cash memory. In this paper, we present a MPEG/Audio decoder for mobile handset applications and implement it on a RISC processor embedding a minimized DSP accelerator. Audio decoding algorithm is splined into two parts; computation intensive and control intensive parts. Those parts we, respectively, allocated to DSP and RISC core, which are designed to run in parallel to increase the processing efficiency. The proposed system implements MP3 and AAC decoders at l7MHz and 24MHz clocks, which are reductions of 48% and 40% of complexities in comparison with implementations on a single RISC processor. The proposed method is adequate for mobile multimedia applications with insufficient cash memory.

• Journal of Korea Society of Digital Industry and Information Management
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• v.15 no.4
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• pp.85-92
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• 2019

This paper presents a SDR-based Long Term Evolution Advanced (LTE-A) Physical Downlink Shared Channel (PDSCH) decoder using a multicore Digital Signal Processor (DSP). For decoder implementation, multicore DSP TMS320C6670 is used, which provides various hardware accelerators such as turbo decoder, fast Fourier transformer and Bit Rate Coprocessors. The TMS320C6670 is a DSP specialized in implementing base station platforms and is not an optimized platform for implementing mobile terminal platform. Accordingly, in this paper, the hardware accelerator was changed to the terminal implementation to implement the LTE-A PDSCH decoder supporting the multi-antenna and the functions not provided by the hardware accelerator were implemented through core programming. Also pipeline using multicore was implemented to meet the transmission time interval. To confirm the feasibility of the proposed implementation, we verified the real-time decoding capability of the PDSCH decoder implemented using the LTE-A Reference Measurement Channel (RMC) waveform about transmission mode 2 and 3.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.42 no.8 s.338
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• pp.11-16
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• 2005

This paper proposes a bit manipulation accelerator (BMA) having application specific instructions, which efficiently supports scrambling, convolutional encoding, puncturing, and interleaving. Conventional DSPs cannot effectively perform bit manipulation functions since かey have multiply accumulate (MAC) oriented data paths and word-based functions. However, the proposed accelerator can efficiently process bit manipulation functions using parallel shift and Exclusive-OR (XOR) operations and bit jnsertion/extraction operations on multiple data. The proposed BMA has been modeled by VHDL and synthesized using the SEC $0.18\mu m$ standard cell library and the gate count of the BMA is only about 1,700 gates. Performance comparisons show that the number of clock cycles can be reduced about $40\%\sim80\%$ for scrambling, convolutional encoding and interleaving compared with existing DSPs.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.2
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• pp.82-92
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• 2008

Recently, many digital signal processing(DSP) applications such as H.264, CDMA and MP3 are predominant tasks for modern high-performance portable devices. These applications are generally computation-intensive, and therefore, require quite complicated accelerator units to improve performance. Designing such specialized, yet fixed DSP accelerators takes lots of effort. Therefore, DSPs with multiple accelerators often have a very poor time-to-market and an unacceptable area overhead. To avoid such long time-to-market and high-area overhead, dynamically reconfigurable DSP architectures have attracted a lot of attention lately. Dynamically reconfigurable DSPs typically employ a multi-functional DSP accelerator which executes similar, yet different multiple kinds of computations for DSP applications. With this type of dynamically reconfigurable DSP accelerators, the time to market reduces significantly. However, integrating multiple functionalities into a single IP often results in excessive control and area overhead. Therefore, delay and power consumption often turn out to be quite excessive. In this thesis, to reduce power consumption of dynamically reconfigurable IPs, we propose a novel fine-grained clock gating scheme, and to reduce size of dynamically reconfigurable IPs, we propose a compact multiplier-less multiplication unit where shifters and adders carry out constant multiplications.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.106-108
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• 2005

High accuracy and stability digital controlled power supply for magnet is developed at PLS. This power supply has three sections. The first section is digital controller including DSP&FPGA and precision ADC, the second section consists of IGBT driver and four quad IGBT switch, and the third section is LC output filter section. AC input voltage of power supply is 3-phase 21V, output current is 0 ${\sim}$ 150 A dc. Switching frequency of four quad IGBT switch is 25 kHz. The output current of power supply has very high accuracy of 100 A step resolution at full range and the stability of +/- 1.5 ppm for short term and +/- 5 ppm for long term. This paper describes characteristics of filter and output current performance improvement after LC output filter at four quad digital power supplies.

• Proceedings of the KIEE Conference
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• 2011.07a
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• pp.1201-1203
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• 2011

이 논문은 가속기에 사용되는 전자석용 전원장치 개발에 대해서 기술하였다. 이 전원장치는 DSP TMS320F2808과 ADCs, FPGA를 이용한 디지털 신호처리 기술을 적용하여 5ppm 이하의 출력 전류 안정도를 가진다. 여기서는 전원장치의 입력 및 출력 필터, 비례적분 보상기 등에 대한 설계, 전원장치 모의실험 결과 및 제작 후 출력 전류의 안정도, 시스템의 주파수 특성 등 여러 성능의 측정 결과에 대하여 기술하였다.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.44 no.5
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• pp.112-117
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• 2007

This paper presents specialized DSP instructions and their hardware architecture for audio coding algorithms, such as the MPEG-2/4 Advanced Audio Coding(AAC), Dolby AC-3, MPEG-2 Backward Compatible(BC), etc. The proposed architecture is specially designed and optimized for the MDCT/IMDCT(Inverse Modified Discrete Cosine Transform), and Huffman decoding of the AAC decoding algorithm. Performance comparisons show a significant improvement compared with TMS320C62x and ASDSP21060 for the MDCT/IMDCT computation. In addition, the dedicated Huffman decoding accelerator performs decoding and preparing operand in only one cycle. The proposed DPU(Data Processing Unit) consists of 107,860 gates and achieves 150 MIPS.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.26 no.7
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• pp.1071-1077
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• 2022

A security SoC that can be used to implement elliptic curve cryptography (ECC) based public-key infrastructures was designed. The security SoC has an architecture in which a hardware accelerator for the elliptic curve digital signature algorithm (ECDSA) is interfaced with the Cortex-A53 CPU using the AXI4-Lite bus. The ECDSA hardware accelerator, which consists of a high-performance ECC processor, a SHA3 hash core, a true random number generator (TRNG), a modular multiplier, BRAM, and control FSM, was designed to perform the high-performance computation of ECDSA signature generation and signature verification with minimal CPU control. The security SoC was implemented in the Zynq UltraScale+ MPSoC device to perform hardware-software co-verification, and it was evaluated that the ECDSA signature generation or signature verification can be achieved about 1,000 times per second at a clock frequency of 150 MHz. The ECDSA hardware accelerator was implemented using hardware resources of 74,630 LUTs, 23,356 flip-flops, 32kb BRAM, and 36 DSP blocks.

• Proceedings of the KIPE Conference
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• 2010.07a
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• pp.444-445
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• 2010

This paper deals with the development of an IPMSM motor drive for NEVs. The drive system consists of 7kW IPMSM motor, DSP-based controller, and MOSFET-based inverter. The controller provides the same accelerator function as the conventional vehicle for an easy NEV drive.