• The Transactions of the Korean Institute of Power Electronics
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• v.8 no.2
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• pp.143-150
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• 2003

An improved MPPT converter with current compensation method for small-scaled PV-applications is presented in this paper. The proposed method implements maximum power point tracking (MPPT) by variable reference current which is continuously changed during one sampling period. Therefore, the Power transferred to the load is increased above 9% by the proposed MPPT converter with current compensation method. As a result, the utilization efficiency of Photovoltaic (PV)-panel can be increased. In addition, as it doesn't use digital signal processor (DSP), this MPPT method has the merits of both a cost efficiency and a simple control circuit design. Therefore, it is considered that the proposed MPPT method is proper to low power, low cost PV-applications. The concept and control principles of the proposed Un moth()d are explained in detail and its validity of the proposed method is verified through several simulated results.

• The Journal of the Acoustical Society of Korea
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• v.16 no.3E
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• pp.56-61
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• 1997

In this paper, we describe a real-time implementation of a multi-channel auido codec system that is based on the MPEG-1 audio algorithm. The major feature of this system is that it has a flexible multi-DSP system that can be adapted for various applications with using up to four TMS320C40 DSPs. The purpose of this paper is to present the problems of the system and is to describe the optimized methods to solve the problems in the view of hardware and software. Our audio codec is composed of an encoder an a decoder system and the bit rate of bitstream is up to 384 kbps. Fast input/output interfaces, DSP overloads, and inter-DSP communications methods with high speed are considered in multi-DSP H/W. Also, to run real-time in S/W, optimizing methods of algorithm are considered. After implementation of system, the subjective assessment method, and 'triple stimulus/hidden reference/double blind' that recommended by ITU-R TG10/3 is adopted for the quality of our system. All test items except one are awarded difference grades(diffgrade) better than 1-. Form the results, multi-channel audio system can be used for HDTV service.

• The Transactions of the Korean Institute of Power Electronics
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• v.15 no.4
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• pp.288-295
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• 2010

Multi-level inverters have drawn much of attention in recent years because it can meet the demand of high power applications and good power quality associated with reduced harmonic distortion. As the number of voltage level increases, field programmable gate arrays (FPGAs) are suitable for the implementation of multi-level modulation algorithm. This paper proposes the implementation method for generating PWM pulses at the three phase diode clamped five-level inverter using FPGA. The strategy for communicating stably the data of three-phase reference voltages between the DSP and FPGA is suggested. The techniques for generating PWM signals based on a multi-carrier modulation method are carried out through the experiments with 32-bit DSP and Cyclone-III FPGA.

• Journal of The Institute of Information and Telecommunication Facilities Engineering
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• v.5 no.1
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• pp.25-36
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• 2006

This paper discusses the implementation and performance evaluation of a DSP-based digital beamformer using the Texas Instrument TMSC6711 DSP processor for smart antenna applications. Two adaptive beamforming algorithms which served as the brain for the beamformer, the Normalized Least-Mean-Square (NLMS) and the Constant Modulus Algorithms (CMA) were embedded into the processor and evaluated. Result shows that the NLMS-based digital beamformer outperforms the CMA-based digital beamformer: 1)For NLMS algorithm, the antenna steers to the direction of the desired user even at low iteration value and the suppression level towards the interferer increases as the number of iteration increase. For CMA algorithm, the beam radiation pattern slowly steers to the desired user as the number of iteration increased, but at arate slower than NLMS algorithm and the sidelobe level is shown to increases as the number of iteration increase. 2) The NLMS algorithm has faster convergence than CMA algorithm and the error convergence for CMA algorithm sometimes is subject to misadjustment.

• Journal of Electrical Engineering and Technology
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• v.3 no.3
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• pp.430-435
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• 2008

In the paper, an algorithm called a Constraint algorithm is proposed to solve the fan-in problem occurred in ADC encoding circuits. The Flash ADC architecture uses a double-base number system (DBNS). The DBNS has known to represent the multi-dimensional logarithmic number system (MDLNS) used for implementing the multiplier accumulator architecture of FIR filter in digital signal processing (DSP) applications. The authors use the DBNS with the base 2 and 3 to represent binary output of ADC. A symmetric map is analyzed first, and then asymmetric map is followed to provide addition read DBNS to DSP circuitry. The simulation results are shown for the Double-Base Integer Encoder (DBIE) of the 6-bit ADC to demonstrate an effectiveness of the Constraint algorithm, using $0.18{\mu}\;m$ CMOS technology. The DBIE’s processing speed of the ADC is fast compared to the FAT tree encoder circuit by 0.95 GHz.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.227-229
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• 2005

This paper proposes a method of implementation of digital convergence platform(DCP) which enable the service of broadcasting, communication, multimedia and home automation. Also digital convergence platform based on MPEG-21 multimedia framework can be a model to provide a distributed electronic commerce environment of multimedia and to manage of it. Platform hardware is implemented using a general purpose CPU and high performance digital signal processor and has peripheral units for network and multi I/O. It is able to run applications of multimedia which has variable formats on DSP. In addition, a personal transaction of multimedia packaged with MPEG-21 multimedia framework is provided on digital convergence platform. Like this, digital convergence platform bring up a new architecture of multimedia systems using a new generation network.

• Proceedings of the IEEK Conference
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• 2001.06b
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• pp.105-108
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• 2001

4 32-bit RISC core is designed for embedded application and DSP. This processor offers low power consumption by fully static operation and compact code size by efficient instruction set. Processor performance is improved by wing conditional instruction execution, block data transfer instruction, multiplication instruction, bunked register file structure. To support compact code size of embedded application, It is capable cf executing both 16-bit instructions and 32-bit instruction through mixed mode instruction conversion Furthermore, for fast MAC operation for DSP applications, the processor has a dedicated hardware multiplier, which can complete a 32-bit by 32-bit integer multiplication within seven clock cycles. These result in high instruction throughput and real-time interrupt response. This chip is implemented with 0.35${\mu}{\textrm}{m}$, 4- metal CMOS technology and consists of about 50K gate equivalents.

• Proceedings of the IEEK Conference
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• 2002.06e
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• pp.227-230
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• 2002

In this paper, we designed and made an image processing board that converts analog NTSC CVBS from CCD camera into digital image, stores it in a memory and accomplishes an appropriate digital image processing suitable to our application. And then loaded it on the self-controlled mobile vehicle and verified its performance by controlling the self-controlled mobile vehicle to avoid obstacles and arrive at the destination through various digital image processes. From the result, the self-controled mobile vehicle system avoided obstacles and got the destination correctly. We knew that designed image processing board is enough to realize the real-time control system.

• Proceedings of the KIEE Conference
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• 1995.11a
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• pp.33-35
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• 1995

Permanent magnet brushless motor is widely used in industrial drive applications due to high efficiency, high power ratio, and easy maintenance. Position and speed sensors required in this dolor increase the drive cost, and reduce the application range. Some papers present the sensorless speed control using DSP with a high processing performance. However, DSP increases the cost, and makes the implementation difficult. This study has performed the sensorless speed control with a microprocessor system which can be easily accessed.

• Journal of Power Electronics
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• v.12 no.2
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• pp.285-293
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• 2012

Multilevel inverters have gained attention in high-power applications due to their numerous advantages in comparison with conventional two-level inverters. In this paper a simplified Space-Vector Modulation (SVM) algorithm for a three-level Neutral-Point Clamped (NPC) inverter is implemented on a Freescale$^{(R)}$ DSP56F8037. The algorithm is based on a simplification of the space-vector diagram for a three-level inverter so that it can be used with a two-level inverter. Once the simplification has been achieved, calculation of the dwell times and the switching sequences are carried out in the same way as for the two-level SVM method. Details of the hardware design are included. Experimental results are analyzed to validate the performance of the simplified algorithm.