• Proceedings of the IEEK Conference
• /
• 2006.06a
• /
• pp.595-596
• /
• 2006

A novel Si via structure is suggested and fabricated for 3D MEMS package using the doped silicon as an interconnection material. Oxide isolations which define Si via are formed simultaneously when fabricating the MEMS structure by using DRIE and oxidation. Silicon Direct Bonding Multi-stacking process is used for stacked package, which consists of a substrate, MEMS structure layer and a cover layer. The bonded wafers are thinned by lapping and polishing. A via with the size of $20{\mu}m$ is fabricated and the electrical and mechanical characteristics of via are under testing.

• Proceedings of the KIEE Conference
• /
• 2005.07c
• /
• pp.2392-2394
• /
• 2005

This paper presents a tuneable bandstop resonator with two possible configurations, it can be used to tune its center frequency, or it can be used to tune its bandwidth. The tuneable bandstop resonator has potential application in microwave communications receivers, where it can be used to tune out interfering signals. The proposed resonator is comb actuated, where the resonator's displacement produces different values of frequency or bandwidth, this is achieved by decoupling electromagnetic energy from a main transmission line. The proposed fabrication process for the resonator is by anodic bonding pyrex glass and tow resistivity silicon, where the comb resonator structure is patterned by deep reactive ion etching (DRIE). This paper presents the resonator and actuator design in both configurations, as well as the fabrication process intended for its development.

• KSTLE International Journal
• /
• v.8 no.2
• /
• pp.26-28
• /
• 2007

Si(100) surfaces were topographically modified i.e. the surfaces were patterned at micro-scale using photolithography and DRIE (Deep Reactive Ion Etching) fabrication techniques. The patterned shapes included micro-pillars and microchannels. After the fabrication of the patterns, the patterned surfaces were chemically modified by coating a thin DLC film. The surfaces were then evaluated for their friction behavior at micro-scale in comparison with those of bare Si(100) flat, DLC coated Si(100) flat and uncoated patterned surfaces. Experimental results showed that the chemically treated (DLC coated) patterned surfaces exhibited the lowest values of coefficient of friction when compared to the rest of the surfaces. This indicates that a combination of both the topographical and chemical modification is very effective in reducing the friction property. Combined surface treatments such as these could be useful for tribological applications in miniaturized devices such as Micro-Electro-Mechanical-Systems (MEMS).

• Journal of the Microelectronics and Packaging Society
• /
• v.17 no.3
• /
• pp.79-84
• /
• 2010

Formation of TSV (Through-Si-Via) with an Au seed layer and Cu filling to the via, simplification of bumping process for three dimensional stacking of Si dice were investigated. In order to produce the via holes, the Si wafer was etched by a DRIE (Deep Reactive Ion Etching) process using $SF_6$ and $C_4F_8$ plasmas alternately. The vias were 40 ${\mu}m$ in diameter, 80 ${\mu}m$ in depth, and were produced by etching for 1.92 ks. On the via side wall, a dielectric layer of $SiO_2$ was formed by thermal oxidation, and an adhesion layer of Ti, and a seed layer of Au were applied by sputtering. Electroplating with pulsed DC was applied to fill the via holes with Cu. The plating condition was at a forward pulse current density of 1000 mA/$dm^2$ for 5 s and a reverse pulse current density of 190 mA/$dm^2$ for 25 s. By using these parameters, sound Cu filling was obtained in the vias with a total plating time of 57.6 ks. Sn bumping was performed on the Cu plugs without lithography process. The bumps were produced on the Si die successfully by the simplified process without serious defect.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.8 no.2
• /
• pp.121-127
• /
• 2008

This paper presents design and fabrication of optimized geometry structure of electrostatic inkjet head. In order to verify effect of geometry shape, we simulate electric field intensity according to the head structure. The electric field strength increases linearly with increasing height of the micro nozzle. As the nozzle diameter decreases, the electric field along the periphery of the meniscus can be more concentrated. We design and fabricate the electrostatic inkjet heads, hole type and pole type, with optimized structure. It was fabricated using thick-thermal oxidation and silicon micromachining technique such as the deep reactive ion etching (DRIE) and chemical wet etching process. It is verified experimentally that the use of the MEMS inkjet head allows a stable and sustainable micro-dripping mode of droplet ejection. A stable micro dripping mode of ejection is observed under the voltages 2.5 kV and droplet diameter is $10\;{\mu}m$.

• Journal of Sensor Science and Technology
• /
• v.16 no.1
• /
• pp.62-67
• /
• 2007

This paper presents a novel MEMS condenser microphone with rigid backplate to enhance acoustic characteristics. The MEMS condenser microphone consists of membrane and backplate chips which are bonded together by gold-tin (Au/Sn) eutectic solder bonding. The membrane chip has 2.5 mm${\times}$2.5 mm, $0.5{\mu}m$ thick low stress silicon nitride membrane, 2 mm${\times}$2 mm Au/Ni/Cr membrane electrode, and $3{\mu}m$ thick Au/Sn layer. The backplate chip has 2 mm${\times}$2 mm, $150{\mu}m$ thick single crystal silicon rigid backplate, 1.8 mm${\times}$1.8 mm backplate electrode, and air gap, which is fabricated by bulk micromachining and silicon deep reactive ion etching. Slots and $50-60{\mu}m$ radius circular acoustic holes to reduce air damping are also formed in the backplate chip. The fabricated microphone sensitivity is $39.8{\mu}V/Pa$ (-88 dB re. 1 V/Pa) at 1 kHz and 28 V polarization voltage. The microphone shows flat frequency response within 1 dB between 20 Hz and 5 kHz.

• Proceedings of the KIEE Conference
• /
• 2011.07a
• /
• pp.1684-1685
• /
• 2011

This paper presents a theoretical and numerical analysis for thermal isolation of silicon micro-structures, especially for a large size with poor thermal conductivity, as well as straightforward solution for such an issue. Additional metal patterns underneath the silicon structures effectively reduces the thermal isolation. Heat transfer mechanism is analyzed using an equivalent circuit of thermal network including plasma, a heat source, heat capacitors, and thermal resistances. The FEM simulation was carried out to investigate the temperature change of silicon micro-structures according to process time. The temperature of silicon micro-structures with 2 ${\mu}m$ thick chrome layer at a steady state is $86^{\circ}C$, an approximately 40% decrease from the silicon microstructure without thin metal ($122^{\circ}C$)

• Transactions on Electrical and Electronic Materials
• /
• v.15 no.2
• /
• pp.91-95
• /
• 2014

This paper presents the structure and process technology of simple and low-cost wafer-level packaging (WLP) for thin film radio frequency (RF) devices. Low-cost practical micromachining processes were proposed as an alternative to high-cost processes, such as silicon deep reactive ion etching (DRIE) or electro-plating, in order to reduce the fabrication cost. Gold (Au)/Tin (Sn) alloy was utilized as the solder material for bonding and hermetic sealing. The small size fabricated WLP of $1.04{\times}1.04{\times}0.4mm^3$ had an average shear strength of 10.425 $kg/mm^2$, and the leakage rate of all chips was lower than $1.2{\times}10^{-5}$ atm.cc/sec. These results met Military Standards 883F (MIL-STD-883F). As the newly proposed WLP structure is simple, and its process technology is inexpensive, the fabricated WLP is a good candidate for thin film type RF devices.

• Proceedings of the Korean Society of Precision Engineering Conference
• /
• 2003.06a
• /
• pp.1186-1190
• /
• 2003

In this paper, a valveless bubble-actuated fluid micropump was has been developed and its performance was tested. The valveless micropump consists of the lower plate, the middle plate, the upper plate and a resistive heater. The lower plate includes the nozzle-diffuser elements and the double-chamber. Nozzle-diffuser elements and a double-chamber are fabricated on the silicon wafer by the DRIE(Deep Reactive Ion Etching) process. The lower plate also has inlet/outlet channels for fluid flow. The middle plate is made of glass and plays the role of the diaphragm. The chamber in the upper plate is filled with deionized water, and which contacts with the resistive heater. The resistive heater is patterned on a silicon substrate by Ti/Pt sputtering. Three plates and the resister heater are laminated by the aligner and bonded in the anodic bonder. Since the bubble is evaporated and condensed periodically in the chamber, the fluid flows from inlet to outlet with respect to the diffusion effect. In order to avoid backflow, the double chamber system is introduced. Analytical and experimental results show the validity of the developed double-chamber micropump.

• Proceedings of the KSME Conference
• /
• 2008.11a
• /
• pp.1869-1873
• /
• 2008

In this work, to make it possible to generate glow discharge in atmospheric pressure condition with relatively high and wide electric field, micro channel reactor is proposed. Si DRIE and Cr deposition by Ebeam evaporation is used to make channel and bottom electrode layer. Upper electrode is made from ITO glass to visualize discharge within micro channel. Fabricated reactor is verified by generating uniform glow plasma with N2 / He gases each as working fluid. The range of gas electric field to generate glow plasma is from about 200 V/cm and upper limit is not observed in tested condition of up to 150 kV/cm. This data shows that micro channel plasma reactor is more versatile. Indirect estimation of electron temperature in this reactor can be inferred that the electron temperature within glow discharge in micro reactor lies $0{\sim}2eV$. This research demonstrates that the reactor is appropriate in application that needs to maintain low temperature condition during chemical process.