• 한국진공학회:학술대회논문집
• /
• 한국진공학회 2008년도 제34회 동계학술대회 초록집
• /
• pp.317-317
• /
• 2008

• 한국정보과학회논문지:시스템및이론
• /
• 제37권1호
• /
• pp.19-26
• /
• 2010

본 논문에서는 차세대 비휘발성램 기술인 스토리지 클래스 메모리(SCM)와 DRAM을 병렬적으로 메인 메모리로서 도입하고, SCM+DRAM 메인 메모리 시스템을 시스템 신뢰성 측면에서 활용한다. 본 시스템에서는 부팅 없는 즉각적인 시스템 온/오프, 프로세스의 동적인 영속성 또는 비영속성의 선택, 그리고 이를 통하여 전원과 소프트웨어 장애로부터의 빠른 복구를 제공한다. 본 논문에서 제안하는 시스템의 장점은 체크포인팅에서의 문제들, 즉 심각한 오버헤드와 복구 지연을 야기하지 않으며, 특히 응용 프로그램에 대한 완전한 투명성을 제공하기 때문에 보편적인 응용 프로그램에 영속성을 제공할 수 있어 실제 환경에 적용되기가 쉽다. 우리는 이를 검증하기 위해 상용 운영체제인 리눅스 커널 2.6.21을 기반으로 시스템을 구현하였고, 실험을 통해 영속성이 지정된 프로세스가 시스템의 오프-온 후 데이터 손실 없이 즉각적으로 실행을 지속하는 것을 알 수 있었으며, 이를 통하여 우리는 본 시스템에서 가용성과 신뢰성이 향상될 수 있음을 확인하였다.

• JSTS:Journal of Semiconductor Technology and Science
• /
• 제7권2호
• /
• pp.67-75
• /
• 2007

To improve low sense margin at low voltage, we propose a negatively driven sensing (NDS) scheme and to solve the problem of WL-to-BL short leakage fail, a variable bitline reference scheme with free-level precharged bitline (FLPB) scheme is adopted. The influence of the threshold voltage offset of NMOS and PMOS transistors in a latch type sense amplifier is very important factor these days. From evaluating the sense amplifier offset voltage distribution of NMOS and PMOS, it is well known that PMOS has larger distribution in threshold voltage variation than that of NMOS. The negatively-driven sensing (NDS) scheme enhances the NMOS amplifying ability. The offset voltage distribution is overcome by NMOS activation with NDS scheme first and PMOS activation followed by time delay. The sense amplifier takes a negative voltage during the sensing and amplifying period. The negative voltage of NDS scheme is about -0.3V to -0.6V. The performance of the NDS scheme for DRAM at the gigabit level has been verified through its realization on 1-Gb DDR2 DRAM chip.

• 한국전기전자재료학회논문지
• /
• 제11권2호
• /
• pp.133-137
• /
• 1998

$(Pb_{0.72}La_{0.28})Ti_{0.93}O_3(PLT(28))$ thin films were fabricated by pulsed laser deposition. PLT films deposited on $Pt/Ti/SiO_2/Si$ at $600^{\circ}C$ had a preferred orientation in (111) plane and at $550^{\circ}C$ had a (100) preferred orientation. We found that (111) preferred oriented films had well grown normal to substrate surface. This PLT(28) thin films of $1{\mu}m$ thickness had dielectric properties of ${\varepsilon}_r$=1300, dielectric $loss{\fallingdotseq}0.03 $. and had charge storage density of 10 [${\mu}C/cm^2$] and leakage current density of less than $10^{-6}[A/cm^2]$ at 100[kV/cm]. These results indicated that the PLT(28) thin films fabricated by pulsed laser deposition are suitable for DRAM capacitor application.

• 대한임베디드공학회논문지
• /
• 제13권3호
• /
• pp.151-160
• /
• 2018

NAND flash memories have the advantages of fast access speed, high density and low power consumption, thus they have increasing demand in embedded system and mobile environment. Despite the low power and fast speed gains of NAND flash memory, DRAM disk buffers were used because of the performance load and limited durability of NAND flash cell. However, DRAM disk buffers are not suitable for limited energy environments due to their high static energy consumption. In this paper, we propose WAP-LRU (Write pattern Analysis based Placement by LRU) hybrid disk buffer management policy. Our policy designates the buffer location in the hybrid memory by analyzing write pattern of the workloads to check the continuity of the page operations. In our simulation, WAP-LRU increased the lifetime of NAND flash memory by reducing the number of garbage collections by 63.1% on average. In addition, energy consumption is reduced by an average of 53.4% compared to DRAM disk buffers.

• 한국진공학회지
• /
• 제4권S1호
• /
• pp.138-144
• /
• 1995

It is commonly believed that high permittivity materials will be necessary for future high density Gbit DRAMs. In a first part, we explain the choice of SrTiO3 by ECR MOCVD for Gbit-scale DRAMs. In a second part, after describing the ECR MOCVD system and presenting the requirements SrTiO3 thin films should meet for use in Gbit-scale DRAMs, the physical and electrical properties of srTiO3 thi film prepared by ECR MOCVD are then studied. A stacked capacitor technology, suitable for use in 1 Gbit DRAM, and comprising high permittivity SrTiO3 thin films prepared by ECR MOCVD at $450^{\circ}C$ on electron beam and RIE patterned RuO2/TiN storage nodes is finally described.

• ETRI Journal
• /
• 제30권4호
• /
• pp.612-614
• /
• 2008

A novel linear switched termination active cross-coupled low-voltage differential signaling (LVDS) transceiver operating at 1.5 GHz clock frequency is presented. On the transmitter side, an active cross-coupled linear output driver and a switched termination scheme are applied to achieve high speed with low current. On the receiver side, a shared pre-amplifier scheme is employed to reduce power consumption. The proposed LVDS transceiver implemented in an 80 nm CMOS process is successfully demonstrated to provide a data rate of 6 Gbps/pin, an output data window of 147 ps peak-to-peak, and a data swing of 196 mV. The power consumption is measured to be 4.2 mW/pin at 1.2 V.

• 대한임베디드공학회논문지
• /
• 제14권2호
• /
• pp.71-78
• /
• 2019

As the capacity of SSDs rapidly increases, the amount of DRAM to keep a mapping table size in SSDs becomes very huge. To address a Demand-based FTL (DFTL) scheme that caches part of mapping entries in DRAM is considered to be a feasible alternative. However, owing to its unpredictable behaviors, DFTL fails to provide consistent I/O response times. In this paper, we a) analyze a root cause that results in fluctuation on read latency and b) propose a new demand-based FTL scheme that ensures guaranteed read response time with low write amplification. By preventing mapping evictions while serving reads, the proposed technique guarantees every host read requests to be done in 2 NAND read operations. Moreover, only with 25% of a cache ratio, the proposed scheme improves random write performance and random mixed performance by 1.65x and 1.15x, respectively, over the traditional DFTL.

• 한국산업융합학회 논문집
• /
• 제24권1호
• /
• pp.69-77
• /
• 2021

The widely used low-cost design methodology for IoT devices is very popular. In such a networked device, memory is composed of flash memory, SRAM, DRAM, etc., and because it processes a large amount of data, memory design is an important factor for system performance. Therefore, each device selects optimized design factors such as function, performance and cost according to market demand. The design of a memory architecture available for low-cost IoT devices is very limited with the configuration of SRAM, flash memory, and DRAM. In order to process as much data as possible in the same space, an architecture that supports parallel processing units is usually provided. Such parallel architecture is a design method that provides high performance at low cost. However, it needs precise software techniques for instruction and data mapping on the parallel architecture. This paper proposes an instruction/data mapping method to support optimized parallel processing performance. The proposed method optimizes system performance by actively using hardware and software parallelism.

• 대한전자공학회:학술대회논문집
• /
• 대한전자공학회 2006년도 하계종합학술대회
• /
• pp.479-480
• /
• 2006