• Journal of Power Electronics
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• v.16 no.5
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• pp.1791-1801
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• 2016

This paper considers a carrier based signal injection method for use in the three shunt sensing inverter (TSSI) for sensorless motor control. It also analyzes the loss according to the injection axis of the voltage signal. To remove both the phase current and rotor position sensors, a sensorless method and a phase current reconstruction method can be simultaneously considered. However, an interaction between the two methods can be incurred when both methods inject voltage signals simultaneously. In this paper, a signal injection based sensorless method with the 120° OFF Discontinuous PWM (DPWM) is implemented in a TSSI to avoid this interaction problem. Since one leg does not have a switching event for one sampling period in the 120° OFF DPWM, the switching loss is altered according to the injection axis. The switching loss in the d-axis injection case can be up to 32% larger than that in the q-axis injection case. Other losses according to the injection axis are also analyzed.

• Proceedings of the KIPE Conference
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• 2018.11a
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• pp.189-190
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• 2018

본 논문에서는 유도전동기의 토크 리플 및 스위칭 손실 저감을 위해 전압변조기법인 공간벡터변조(Space Vector Pulse Width Modulation, SVPWM) 기법과 불연속전압변조(Discontinuous Pulse Width Modulation, DPWM) 기법을 혼합하여 사용하는 새로운 변조기법을 제안한다. 제안하는 방식은 지령전압이 최대인 부근에서 SVPWM 기법을 사용하며, 나머지 구간에서는 DPWM 기법을 적용한다. 전 구간 단일기법을 적용할 때와 비교하여 제안하는 방식은 토크 리플 및 스위칭 손실을 효율적으로 저감시킬 수 있으며 시뮬레이션을 통해 타당성을 검증한다.

• Journal of Power Electronics
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• v.17 no.3
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• pp.821-834
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• 2017

This paper reports on a single-inductor multiple-output step-up converter with digital control. A systematic analog-to-digital-controller design is explained. The number of digital blocks in the feedback path of the proposed converter has been decreased. The simpler digital pulse-width modulation (DPWM) architecture is then utilized to reduce the power consumption. This architecture has several advantages because counters and a complex digital design are not required. An initially designed unit-delay cell is adopted recursively for the construction of coarse, intermediate, and fine delay blocks. A digital limiter is then designed to allow only useful code for the DPWM. The input voltage is 1.8 V, whereas output voltages are 2 V and 2.2 V. A co-simulation was also conducted utilizing PowerSim and Matlab/Simulink, whereby the 55 nm process was employed in the experimental results to evaluate the performance of the architecture.

• Journal of Korea Society of Industrial Information Systems
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• v.20 no.1
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• pp.1-7
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• 2015

In this paper, a 12-bit high resolution, power and area efficiency hybrid digital pulse width modulator (DPWM) with process and temperature (PT) calibration has been proposed for digital controlled DC-DC converters. The hybrid structure of DPWM combines a 6-bit differential tapped delay line ring-mux digital-to-time converter (DTC) schema and a 6-bit counter-comparator DTC schema, resulting in a power and area saving solution. Furthermore, since the 6-bit differential delay line ring oscillator serves as the clock to the high 6-bit counter-comparator DTC, a high frequency clock is eliminated, and the power is significantly saved. In order to have a simple delay cell and flexible delay time controllability, a voltage controlled inverter is adopted to build the deferential delay cell, which allows fine-tuning of the delay time. The PT calibration circuit is composed of process and temperature monitors, two 2-bit flash ADCs and a lookup table. The monitor circuits sense the PT (Process and Temperature) variations, and the flash ADC converts the data into a digital code. The complete circuits design has been verified under different corners of CMOS 0.18um process technology node.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.29 no.3
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• pp.69-80
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• 2015

This paper is writing about developing magnet power supply. It is very important for power supply to obtain output current in high precision and high stability. As a switching noise and a power noise are the cause of disrupting the stability of output current, to remove these at the front end, low pass filter with 300Hz cutoff frequency is designed and placed. And also to minimize switching noise of the current into magnet and to stop abrupt fluctuations, output filter should be designed, when doing this, we design it by considering load has high value inductance. As power supply demands the stability of less than 5ppm, high precision 24bit(300nV/bit) analog digital converter is needed. As resolving power of 24bit(300nV/bit) analog digital converter is high, it is also very important to design the input stage of analog digital converter. To remove input noise, 4th order low pass filter is composed. Due to the limitation of clock, to minimize quantization error between 15bit DPWM and output of ADC having 24bit resolving power, ${\Sigma}-{\Delta}$ modulation is used and bit contracted DPWM is constituted. And before implementing, to maximize efficiency, simulink is used.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.109-110
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• 2017

본 논문에서는 듀얼 액티브 브릿지에서 SPWM(Single Pulse Width Modulaton)과 DPWM(Dual Pulse Witdh Modulation)을 적용하였을 때, 인덕터 전류의 특성을 비교하고자 한다. 인덕터 전류의 특성을 이론적으로 분석하고, 실험을 통해서 결과를 분석하였다.

• Journal of Power Electronics
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• v.18 no.3
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• pp.702-713
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• 2018

Power loss reduction and total harmonic distortion(THD) minimization are two important goals of improving three-level inverters. In this paper, an optimized pulse width modulation (PWM) strategy that can reduce switching losses and balance the neutral point with an optional THD of three-level neutral-point-clamped inverters is proposed. An analysis of the two-level discontinuous PWM (DPWM) strategy indicates that the optimal goal of the proposed PWM strategy is to reduce switching losses to a minimum without increasing the THD compared to that of traditional SVPWMs. Thus, the analysis of the two-level DPWM strategy is introduced. Through the rational allocation of the zero vector, only two-phase switching devices are active in each sector, and their switching losses can be reduced by one-third compared with those of traditional PWM strategies. A detailed analysis of the impact of small vectors, which correspond to different zero vectors, on the neutral-point potential is conducted, and a hysteresis control method is proposed to balance the neutral point. This method is simple, does not judge the direction of midpoint currents, and can adjust the switching times of devices and the fluctuation of the neutral-point potential by changing the hysteresis loop width. Simulation and experimental results prove the effectiveness and feasibility of the proposed strategy.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.2
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• pp.167-174
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• 2015

This study describes how digital time delay deteriorates control performance in zero voltage switching (ZVS) phase-shifted full bridge (PSFB) converter. The small-signal model of the ZVS PSFB converter is derived from the buck-converter small-signal model. Digital time delay effects have been considered according to the digital sampling methods. The analysis verifies that digital time delays reduce the stability margin of the converter, and the double sampling technique exhibits better performance than the single sampling technique. Both simulation and experimental results based on 250 W ZVS PSFB confirm the validity of the analyses performed in the study.

• Proceedings of the KIPE Conference
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• 2017.11a
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• pp.73-74
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• 2017

본 논문에서는 H7 인버터와 DPWM 기반의 개선된 변조 기법을 이용한 2-레벨 인버터의 커먼 모드(Common Mode) 전압 저감 방법을 제안한다. 기존의 H7 인버터를 이용한 커먼 모드 전압 저감 방법은 스위칭 신호 구현을 위해 추가적인 논리회로가 필요하고, 일부 영역에서 커먼 모드 전압 저감이 이루어지지 않는 문제점이 있다. 제안하는 방법은 옵셋(Offset) 전압을 이용한 변조 방식을 사용하여 3상 인버터의 스위칭 신호를 생성하고, 3상의 지령 값을 이용하여 7번째 스위치의 스위칭 패턴을 결정한다. 이를 통해 추가적인 논리 회로 없이 하나의 캐리어만을 이용하여 모든 스위치의 스위칭 신호를 구현하며, 모든 영역에서 커먼 모드 전압 저감이 이루어지도록 하였다. 제안된 방법의 커먼 모드 전압 저감, 출력 상전류 왜곡 특성에 대한 성능을 시뮬레이션을 통해 검증하였다.

• Journal of Power Electronics
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• v.13 no.4
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• pp.600-608
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• 2013

This paper analyzes the effect of the admittance component for the digitally controlled single-phase bridgeless power factor correction (PFC) converter. To do this, it is shown how the digital delay effects such as the digital pulse-width modulation (DPWM) and the computation delays restrict the bandwidth of the converter. After that, the admittance effect of the entire digital control system is analyzed when the bridgeless PFC converter which has the limited bandwidth is connected to the grid. From this, the waveform distortion of the input current is explained and the compensation method for the admittance component is suggested to improve the quality of the input current. Both the simulations and the experiments are performed to verify the analyses taken in this paper for the 1 kW bridgeless PFC converter prototype.