• Journal of Power Electronics
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• v.17 no.5
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• pp.1372-1381
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• 2017

This paper presents a high-side switch driver IC capable of improving the current sensing accuracy and providing reverse battery protection. Power semiconductor switches used to replace relay switches are encumbered by two disadvantages: they are prone to current sensing errors and they require additional external protection circuits for reverse battery protection. The proposed IC integrates a gate driver and current sensing blocks, thus compensating for these two disadvantages with a single IC. A p-sub-based 90-V $0.13-{\mu}m$ bipolar-CMOS-DMOS (BCD) process is used for the design and fabrication of the proposed IC. The current sensing accuracy (error ${\leq}{\pm}5%$ in the range of 0.1 A-6.5 A) and the reverse battery protection features of the proposed IC were experimentally tested and verified.

• Proceedings of the KIEE Conference
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• 1994.07b
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• pp.1451-1453
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• 1994

A monolithic current limiting power MOSFET, which may be easily fabricated by the conventional DMOS process, is proposed. The proposed current limiting MOSFET consists of main power cells, sensing cells, and NPN lateral bipolar transistor so that users can adjust the current limiting levels with only one external resistor. The behaviors of the proposed device are numerically simulated and analyzed by 2-D device simulator MEDICI and mixed-mode simulator CA-AAM(Circuit Analysis Advanced Application Module).

• JSTS:Journal of Semiconductor Technology and Science
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• v.8 no.3
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• pp.227-231
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• 2008

A latchup-free design based on the lateral diffused MOS (LDMOS) adopting the "Darlington" approaches was designed. The use of Darlington configuration as the trigger circuit results in the reduction of the size of the circuit when compared to the conventional inverter driven RC-triggered MOSFET ESD power clamp circuits. The proposed clamp was fabricated using a $0.35{\mu}m$ 60V BCD (Bipolar CMOS DMOS) process and the performance of the proposed clamp was successfully verified by TLP (Transmission Line Pulsing) measurements.

• Journal of the Institute of Electronics Engineers of Korea SP
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• v.46 no.3
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• pp.75-88
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• 2009

This paper presents a video quality assessment method based on quality degradation factors of real-time multimedia streaming services. The video quality degradation is caused by video source compression and network states. In this paper, we propose a blocky metric on an image domain to measure quality degradation by video compression. In this paper, the proposed boundary strength index for the blocky metric is defined by ratio of the variation of two pixel values adjacent to $8{\times}8$ block boundary and the average variation at several pixels adjacent to the two boundary pixels. On the other hand, unnatural image movement caused by network performance deterioration such as jitter and delay factors can be observed. In this paper, a temporal-Jerkiness measurement method is proposed by computing statistics of luminance differences between consecutive frames and play-time intervals between frames. The proposed final Perceptual Video Quality Metric (PVQM) is proposed by consolidating both blocking strength and temporal-jerkiness. To evaluate performance of the proposed algorithm, the accuracy of the proposed algorithm is compared with Difference of Mean Opinion Score (DMOS) based on human visual system.

• Applied Chemistry for Engineering
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• v.19 no.2
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• pp.222-227
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• 2008

In this work we have studied the antifouling properties of the hydrophobic sol-gel modified sensing membrane and its optical properties for sensor application. E. coli JM109, B. cereus 318 and P. pastoris X-33 were cultivated in confocal cultivation dishes with glass surface, respectively. The glass surface was coated with the hydrophobic sol-gels prepared by the dimethoxy-dimethyl-silane (DiMe-DMOS) and tetramethyl-orthosilicate (TMOS). After cultivation, microorganisms adhered on the surface coated with sol-gels and glass surface were dyed by gram-staining method and the numbers of microorganisms were analyzed based on the image data of the scanning electronic microscope (SEM). A great number of microorganisms, about $2{\sim}3{\times}10^4/mm^2$, was adhered on the glass surfaces which no hydrophobic sol-gels were coated. However, the antifouling effect of the hydrophobic sol-gels was large, that microorganisms of less than $200{\sim}300/mm^2$ were adhered on the coated glass surface. The performance of the sensing membranes for detection of pH and dissolved oxygen was enhanced by recoating the light insulation layer prepared with the mixture of the hydrophobic sol-gel and graphite particles.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.11C
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• pp.655-661
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• 2011

The transmission issues for the scalable video coding extension of H.264/AVC (H.264 SVC) video has been widely studied. In this paper, we propose an objective video-quality assessment metric based on no-reference for H.264 SVC using scalability information. The proposed metric estimate the perceptual video-quality reflecting error conditions with the consideration of the motion vectors, error propagation patterns with the hierarchical prediction structure, quantization parameters, and number of frame which damaged by packet loss. The proposed metric reflects the human perceptual quality of video and we evaluate the performance of proposed metric by using correlation relationship between differential mean opinion score (DMOS) as a subjective quality and proposed one.

• Journal of IKEEE
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• v.15 no.1
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• pp.37-42
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• 2011

In this paper, the high-voltage novel devices have been fabricated by 0.35 um BCD (Bipolar-CMOS-DMOS) process. Electrical characteristics of 20 V level BJT device, 30/60 V HV-CMOS, and 40/60 V LDMOS are analyzed. Also, the vertical/lateral BJT with the high-current gain and LIGBT with the high-voltage are proposed. In the experimental results, vertical/lateral BJT has breakdown voltage of 15 V and current gain of 100. The proposed LIGBT with the high-voltage has breakdown voltage of 195 V, threshold voltage of 1.5 V, and Vce, sat of 1.65 V.

• Phonetics and Speech Sciences
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• v.10 no.1
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• pp.39-48
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• 2018

A typical statistical parametric speech synthesis (text-to-speech, TTS) system consists of separate modules, such as a text analysis module, an acoustic modeling module, and a speech synthesis module. This causes two problems: 1) expert knowledge of each module is required, and 2) errors generated in each module accumulate passing through each module. An end-to-end TTS system could avoid such problems by synthesizing voice signals directly from an input string. In this study, we implemented an end-to-end Korean TTS system using Google's Tacotron, which is an end-to-end TTS system based on a sequence-to-sequence model with attention mechanism. We used 4392 utterances spoken by a Korean female speaker, an amount that corresponds to 37% of the dataset Google used for training Tacotron. Our system obtained mean opinion score (MOS) 2.98 and degradation mean opinion score (DMOS) 3.25. We will discuss the factors which affected training of the system. Experiments demonstrate that the post-processing network needs to be designed considering output language and input characters and that according to the amount of training data, the maximum value of n for n-grams modeled by the encoder should be small enough.

• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.25 no.2
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• pp.80-86
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• 2011

This paper presents an integrated variable amplitude high voltage pulse generation circuit with low power and small size for driving industrial piezoelectric printer heads. To solve the problems of large size and power overhead of conventional pulse generators that usually assembled with multiple high-cost discrete ICs on a PCB board, we have designed a new integrated circuit (IC) chip. Since all the functions are integrated on to a single-chip it can achieve low cost and control the high-voltage output pulse with variable amplitudes as well. It can also digitally control the rising and falling times of an output high voltage pulse by using programmable RC time control of the output buffer. The proposed circuit has been designed and simulatedd in a 180[nm] Bipolar-CMOS-DMOS (BCD) technology using HSPICE and Cadence Virtuoso Tools. The proposed single-chip pulse generation circuit is suitable for use in industrial printer heads requiring a variable high voltage driving capability.