• 방송공학회논문지
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• 제14권2호
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• pp.197-209
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• 2009

스테레오 영상은 기존의 영상과는 달리 사용자에게 깊이감을 제공한다. 따라서 스테레오 영상을 평가하기 위해서는 새로운 화질평가 모델이 필요하다. 본 논문에서는 스테레오 영상을 위한 객관적 화질평가 방법을 제안한다. 제안된 화질평가 방법은 기존의 화질평가 모델을 기반으로 하여 블로킹 현상과 경계 영역에서의 열화 현상을 검출하였으며, 깊이 정보를 고려하여 시점 간 화질 격차 검출을 통해 알고리즘의 성능을 높이고자 하였다. 제안된 알고리즘의 성능 확인을 위해 스테레오 영상의 주관적 화질평가를 수행하였으며 주관적 화질평가와의 상관성 측면에서 제안 알고리즘이 PSNR에 비해 우수함을 확인하였다.

• ETRI Journal
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• 제38권2호
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• pp.272-279
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• 2016

In this paper, a new structure for an advanced high holding voltage silicon controlled rectifier (AHHVSCR) is proposed. The proposed new structure specifically for an AHHVSCR-based electrostatic discharge (ESD) protection circuit can protect integrated circuits from ESD stress. The new structure involves the insertion of a PMOS into an AHHVSCR so as to prevent a state of latch-up from occurring due to a low holding voltage. We use a TACD simulation to conduct a comparative analysis of three types of circuit - (i) an AHHVSCR-based ESD protection circuit having the proposed new structure (that is, a PMOS inserted into the AHHVSCR), (ii) a standard AHHVSCR-based ESD protection circuit, and (iii) a standard HHVSCR-based ESD protection circuit. A circuit having the proposed new structure is fabricated using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology. The fabricated circuit is also evaluated using Transmission-Line Pulse measurements to confirm its electrical characteristics, and human-body model and machine model tests are used to confirm its robustness. The fabricated circuit has a holding voltage of 18.78 V and a second breakdown current of more than 8 A.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2015년도 제46회 하계학술대회
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• pp.1018-1019
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• 2015

Recently, standby power reduction techniques of AC/DC adaptor were developed, consuming power almost arrived to 300mW level. The standby power losses are composed of the input filter loss 11.8mW, the control IC for AC/DC adaptor 18mW, the switching loss 9.53mW and the feedback loss 123mW. And there are the standby power reduction techniques. In this paper, in order to reduce the standby power of SMPS more, the loss due to a voltage difference between input and output is reduced by the control circuit which is composed of the low voltage driving circuit and voltage regulator. The low voltage driving circuit operates on the low voltage of input and off the high voltage. The low voltage driving IC was produced by the $1.0{\mu}m$, high voltage DMOS process.

• ETRI Journal
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• 제37권6호
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• pp.1188-1198
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• 2015

In this paper, a multi-time programmable (MTP) cell based on a $0.18{\mu}m$ bipolar-CMOS-DMOS backbone process that can be written into by using dual pumping voltages - VPP (boosted voltage) and VNN (negative voltage) - is used to design MTP memories without high voltage devices. The used MTP cell consists of a control gate (CG) capacitor, a TG_SENSE transistor, and a select transistor. To reduce the MTP cell size, the tunnel gate (TG) oxide and sense transistor are merged into a single TG_SENSE transistor; only two p-wells are used - one for the TG_SENSE and sense transistors and the other for the CG capacitor; moreover, only one deep n-well is used for the 256-bit MTP cell array. In addition, a three-stage voltage level translator, a VNN charge pump, and a VNN precharge circuit are newly proposed to secure the reliability of 5 V devices. Also, a dual memory structure, which is separated into a designer memory area of $1row{\times}64columns$ and a user memory area of $3rows{\times}64columns$, is newly proposed in this paper.

• ETRI Journal
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• 제39권5호
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• pp.746-755
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• 2017

In this paper, an electrostatic discharge (ESD) protection circuit is designed for use as a 12 V power clamp by using a parasitic-diode-triggered silicon controlled rectifier. The breakdown voltage and trigger voltage ($V_t$) of the proposed ESD protection circuit are improved by varying the length between the n-well and the p-well, and by adding $n^+/p^+$ floating regions. Moreover, the holding voltage ($V_h$) is improved by using segmented technology. The proposed circuit was fabricated using a $0.18-{\mu}m$ bipolar-CMOS-DMOS process with a width of $100{\mu}m$. The electrical characteristics and robustness of the proposed ESD circuit were analyzed using transmission line pulse measurements and an ESD pulse generator. The electrical characteristics of the proposed circuit were also analyzed at high temperature (300 K to 500 K) to verify thermal performance. After optimization, the $V_t$ of the proposed circuit increased from 14 V to 27.8 V, and $V_h$ increased from 5.3 V to 13.6 V. The proposed circuit exhibited good robustness characteristics, enduring human-body-model surges at 7.4 kV and machine-model surges at 450 V.

• Journal of Power Electronics
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• 제12권6호
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• pp.886-894
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• 2012

This paper presents a secondary-side, dual-mode feedback LLC resonant controller IC with dynamic PWM dimming for LED backlight units. In order to reduce the cost, master and slave outputs can be generated simultaneously with a single LLC resonant core based on dual-mode feedback topologies. Pulse Frequency Modulation (PFM) and Pulse Width Modulation (PWM) schemes are used for the master stage and slave stage, respectively. In order to guarantee the correct dual feedback operation, Phased-Locked Loop (PLL)-based automatic duty control circuit is proposed in this paper. The chip is fabricated using $0.35{\mu}m$ Bipolar-CMOS-DMOS (BCD) technology, and the die size is $2.5mm{\times}2.5mm$. The frequency of the gate driver (GDA/GDB) in the clock generator ranges from 50 to 425 kHz. The current consumption of the LLC resonant controller IC is 40 mA for a 100 kHz operation frequency using a 15 V supply. The duty ratio of the slave stage can be controlled from 40% to 60% independent of the frequency of the master stage.

• 한국전기전자재료학회논문지
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• 제22권10호
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• pp.801-807
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• 2009

In this paper, we propose a novel shoot-through protection circuit and pulse generator for half-bridge driver IC. We designed a robust half-bridge driver IC over a variation of processes and power supplies. The proposed circuit is composed a delay circuit using a beta-multiplier reference. The proposed circuit has a lower variation rate of dead time and pulse-width over variation of processes and supply voltages than the conventional circuit. Especially, the proposed circuit has more excellent pulse-width matching of set and reset signals than the conventional circuit. Also, the proposed pulse generator is prevented from fault operations using a logic gate. Dead time and pulse-width of the proposed circuit are typical 250 ns, respectively. The variation ratio is 68%(170 ns) of maximum over variation of processes and supply voltages. The proposed circuit is designed using $1\;{\mu}m$ 650 V BCD (Bipolar, CMOS, DMOS) process parameter, and the simulations are carried out using Spectre simulator of Cadence corporation.

• Journal of Information Display
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• 제13권2호
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• pp.73-82
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• 2012

In this paper, a light-emitting diode (LED) backlight driver integrated circuit (IC) for medium-sized liquid crystal displays (LCDs) is proposed. In the proposed IC, a linear current regulator with matched internal resistors and an adaptive phase-shifted pulse-width modulation (PWM) dimming controller are also proposed to improve LED current uniformity and reliability. The double feedback loop control boost converter is used to achieve high power efficiency, fast transient characteristic, and high dimming frequency and resolution. The proposed IC was fabricated using the 0.35 ${\mu}m$ bipolar-CMOS-DMOS (BCD) process. The LED current uniformity and LED fault immunity of the proposed IC were verified through experiments. The measured power efficiency was 90%; the measured LED current uniformity, 97%; and the measured rising and falling times of the LED current, 86 and 7 ns, respectively. Due to the fast rising and falling characteristics, the proposed IC operates up to 39 kHz PWM dimming frequency, with an 8-bit dimming resolution. It was verified that the phase difference between the PWM dimming signals is changed adaptively when LED fault occurs. The experiment results showed that the proposed IC meets the requirements for the LED backlight driver IC for medium-sized LCDs.

• The Journal of the Acoustical Society of Korea
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• 제14권1E호
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• pp.30-38
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• 1995

본 논문에서는 이동통신망에서 신호 가산방식을 이용한 삼자회의에서의 음성 부호화기 성능을 평가하였다. 두 사람의 섞인 목소리가 다른 회의 참가자에게 전달되는 신호 가산방식은 가장 자연스러운 삼자회의 방식이지만, 아직까지 두 사람의 섞인 목소리를 부호화할 수 있는 유용한 방법은 없다. 본 논문에서는 삼자회의에 신호 가산방식을 적용하기 위해 QCELP, VSELP, RPE-LTP 보코도를 구현하여 평가를 수행하였다. 또한 두 화자의 목소리가 섞인 음성신호에 대한 부호화기의 성능평가를 위해 기존의 음질 평가법을 그대로 사용할 수 없으므로, 본 논문에서는 두 가지 주관적 평가법을 제안하였다. 제안된 방법은 문장 식별법(SD)과 수정된 DMOS(MDOMS) 방법이다. 실험결과에 의하면 VSELP 보코더의 출력음질이 다른 두 보코더에 비해 좋게 나타났다.

• 한국콘텐츠학회논문지
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• 제5권5호
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• pp.202-210
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• 2005

지방자치단체의 관광정보 웹사이트는 정보의 갱신 및 시의적절한 관광정보 공급에 있어 비효율적으로 운영되고 있으며, 관광정보 웹사이트도 체계적이지 못하다. 공공 관광 웹 사이트의 성공적인 운용은 공공성의 유지와 웹 사이트의 지속가능성을 동시에 성취할 수 있는 전략을 수립하는 것이다. 이러한 전략을 위해서는 관광객의 동기와 관광정보검색의 태도에 미치는 영향을 파악하여야 한다. 따라서 본 연구는 관광동기가 정보검색에 미치는 영향을 파악하기 위하여 정보검색모형을 제시하고 이를 실증적으로 분석하고자 한다. 분석결과는 따르면, 활동형 동기는 목적형 정보, 즉 레저/편의시설, 교육/기능성 정보의 중요성에 정(+)의 효과를 가지며, 탈출형 동기는 기본정보의 중요성에 정(+)의 효과를 가진다. 이러한 결과는 관광동기에 따른 검색정보의 상이함으로 인하여 관광목적지 선택에 적용할 수 있는 전략 수립에 한계가 있으며, 관광정보시스템은 목적형 정보를 구조화함으로써 활동형 관광동기 관광객들을 관심집단으로 조직화하는 방향으로 개선되어야 할 것으로 나타났다.