• Journal of the Institute of Electronics Engineers of Korea SP
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• v.43 no.3 s.309
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• pp.92-99
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• 2006

In this paper, a low-power deblocking filter structure for H.264 video coding algorithm is proposed. By sharing addition hardware for common filter coefficients, we have designed an efficient deblocking filter structure. Proposed deblocking filter utilizes MUX and DEMUX circuits for input data sharing and shows 44.2% reduction for add operation. In the HDL coding simulation and FPGA implementation, we achieved 19.5% and 19.4% gate count reduction, respectively, comparison with the conventional deblocking filter structure. Due to its efficient processing scheme, the proposed structure can be widely used in H.264 encoding and decoding SoC.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.7A
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• pp.535-541
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• 2005

This paper proposes a hybrid optical lines composed of single-mode fiber(SMF) and multi-mode fiber(MMF) for gigabit-capable Passive Optical Network(GPON) using a WDM method with a single light source per each channel, and reports the results of transmission performance the proposed lines. The transmission link uses a direct modulated DFB-LD for high speed downstreams at the optical line terminal(OLT) of central office(CO) and a low cost SFP type transceiver for low-speed upstream in optical network unit(ONU). To split or combine the transmission channels, wavelength MUX/DEMUX are used in the optical line section, and MMFs not longer than 1 km are attached to the SMF lines at the ONU side of the WDM-PON links. We have performed the transmission experiment on the downstream of 2.5 Gbit/s, and 1.25 Gbit/s, and the upstream of 1.25 Gbit/s, and 622 Mbit/s which are recommended by ITU-T G.984.2. The transmission margin and feasibility of the proposed links have been tested to be suitable up to 2.5 Gbit/s transmission.

• Journal of IKEEE
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• v.10 no.2 s.19
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• pp.128-133
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• 2006

This paper describes a high speed interface circuit using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that converts redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, the proposed 1:4 DEMUX (demultiplexer, serial-parallel converter), was designed using a 0.35um standard CMOS technology. Proposed DEMUX is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW. The operating speed of this circuit is limited by the maximum frequency which the 0.35um process has. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 10Gb/s in submicron process of high operating frequency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.5
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• pp.58-64
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• 2008

A 6Gbps 1:2 demultiplexer(DEMUX) IC using $0.18{\mu}m$ CMOS was designed and fabricated. For high speed performance current mode logic(CML) flipflop was used and inductive peaking technology was used so as to obtain higher speed than conventional Current mode logic flipflop. On-chip spiral inductor was designed to maximize the inductive peaking effect using stack structure. Total twelve inductors of $100{\mu}m^2$ area increase was used. The measurement was processed on wafer and 1:2 demultiplexer with and without micro stacked spiral inductors were compared. For 6Gbps data rate measurement, eye width was improved 7.27% and Jitter was improved 43% respectively. Power consumption was 76.8mW and eye height was 180mV at 6 Gbps

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.87-97
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• 2016

This work proposes a time-shared 10b DAC based on a two-step resistor string to minimize the effective area of a DAC channel for driving each AMOLED display column. The proposed DAC shows a lower effective DAC area per unit column driver and a faster conversion speed than the conventional DACs by employing a time-shared DEMUX and a ROM-based two-step decoder of 6b and 4b in the first and second resistor string. In the second-stage 4b floating resistor string, a simple current source rather than a unity-gain buffer decreases the loading effect and chip area of a DAC channel and eliminates offset mismatch between channels caused by buffer amplifiers. The proposed 1-to-24 DEMUX enables a single DAC channel to drive 24 columns sequentially with a single-phase clock and a 5b binary counter. A 0.9pF sampling capacitor and a small-sized source follower in the input stage of each column-driving buffer amplifier decrease the effect due to channel charge injection and improve the output settling accuracy of the buffer amplifier while using the top-plate sampling scheme in the proposed DAC. The proposed DAC in a $0.18{\mu}m$ CMOS shows a signal settling time of 62.5ns during code transitions from '$000_{16}$' to '$3FF_{16}$'. The prototype DAC occupies a unit channel area of $0.058mm^2$ and an effective unit channel area of $0.002mm^2$ while consuming 6.08mW with analog and digital power supplies of 3.3V and 1.8V, respectively.

• Proceedings of the IEEK Conference
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• 2005.11a
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• pp.699-702
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• 2005

This paper describes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit and decoding circuit. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 DEMUX (demultiplexer) was designed using a 0.35um standard CMOS technology. Proposed circuit is achieved an operating speed of 4.5Gb/s with a supply voltage of 3.3V and with power consumption of 53mW.

• 한국정보통신설비학회:학술대회논문집
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• 2007.08a
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• pp.386-389
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• 2007

TV technology started from black and white TV. Color TV invented and users request more realistic TV technology. The next technology is 3DTV. For 3DTV, 3D display technology, 3D coding technology, digital mux/demux technology in broadcast and 3D video acquisition are needed. Moreover, Almost every contents now exist are 2D contents. It causes necessity to convert from 2D to 3D. This article describes 2D/3D conversion algorithm and H/W platform on FPGA board. Time difference makes 3D effect and convolution filter increased the effect. Distorted image and original image give 3D effect. The algorithm is shown on 3D display. The display device shows 3D effect by parallax barrier method and has FPGA board.

• Proceedings of the KIEE Conference
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• 2005.05a
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• pp.148-151
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• 2005

This paper proposes a high speed interface using redundant multi-valued logic for high speed communication ICs. This circuit is composed of encoding circuit that serial binary data are received and converted into parallel redundant multi-valued data, and decoding circuit that convert redundant multi-valued data to parallel binary data. Because of the multi-valued data conversion, this circuit makes it possible to achieve higher operating speeds than that of a conventional binary logic. Using this logic, a 1:4 demultiplexer (DEMUX, serial-parallel converter) IC was designed using a 0.35${\mu}m$ standard CMOS Process. Proposed demultiplexer is achieved an operating speed of 3Gb/s with a supply voltage of 3.3V and with power consumption of 48mW. Designed circuit is limited by maximum operating frequency of process. Therefore, this circuit is to achieve CMOS communication ICs with an operating speed greater than 3Gb/s in submicron process of high of operating frequency.

• Proceedings of the KIEE Conference
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• 2005.10b
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• pp.409-411
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• 2005

본 논문에서는 HD급 멀티미디어 streaming을 처리할 수 있는 DSP 플랫폼을 개발하였다. DSP 플랫폼은 Tl사의 C6400계열 DSP를 사용하였고 다채널의 오디오와 HD급 화질의 비디오_ 데이터를 처리할 수 있다. DSP가 decoder의 기능을 부담함으로써 하드웨어의 재구성이 용이하며 코덱을 다운로드하기 때문에 유연한 멀티미디어 컨텐츠의 재생이 가능하다. 개발한 DSP 플랫폼을 호스트 PC에 설치하여 PC로부터 DSP Configuration 파일과 멀티미디어 스트리밍 데이터를 전송받는 구조를 가진다. 소프트웨어는 실시간으로 demux를 실행하여 오디와 비디오_ 데이터를 분리하석 DSP 플랫폼의 외부메모리에 저장하고 동시에 비디오와 오디오의 디코딩을 실행한다. 오디오와 비디오 데이터의 버퍼 언더런/오버런을 극할 수 있는 buffer control 기법을 적용하였다. 호스트 PC에서 DSP 플랫폼으로의 스트리밍을 하기 위하여 Open Architecture 기반의 Windows OS에서 스트리밍 서비스 프로그램을 구현 하였다. 마지막으로 MPEG-2 video MP@ML인 비디오 코덱과 5.1ch 48kHz AC3인 오디오 코덱으 구성된 streaming 데이터를 사용하여 DSP 플랫폼을 검증하였다.

• Proceedings of the Optical Society of Korea Conference
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• 2000.02a
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• pp.78-79
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• 2000

재구성이 가능한 광 크로스-커넥트(optical cross connect)는 전광 네트워크를 구성하기 위한 핵심소자 중의 하나이다. 일반적인 구조의 파장분배기는 공간분할 스위치(space division switch)를 두 쌍의 파장 다중화기(multiplexer)와 역다중화기(demultiplexer)의 가운데에 삽입하여 구현된다$^{(1)}$ . 최근에, 광섬유 브래그 격자와 광스위치 쌍을 직렬 연결하여 재구성이 가능한 광 크로스-커넥트가 제안되었다$^{(2)}$ . 그러나, 이 구조는 광신호에 따라 광섬유 브래그 격자에 반사되면서 겪는 광스위치에 의한 삽입손실이 다르다는 문제점이 있다. 이러한 문제를 해결하기 위하여 본 논문에서는 한 쌍의 파장 다중화기/역다중화기와 파장가변 광섬유 브래그 격자를 이용한 새로운 구조의 광 크로스-커넥트를 제안하고자 한다. 또한, 제안된 구조는 일반적인 구조의 파장분배기에 비해 파장 다중화기/역다중화기의 개수를 반으로 줄일 수 있는 장점이 있다. (중략)