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Low-power Structure for H.264 Deblocking Filter  

Jang Young-Beom (College of Engineering, Sangmyung University)
Oh Se-Man (College of Engineering, Sangmyung University)
Park Jin-Su (College of Engineering, Sangmyung University)
Han Kyu-Hoon (College of Engineering, Sangmyung University)
Kim Soo-Hong (College of Engineering, Sangmyung University)
Publication Information
Journal of the Institute of Electronics Engineers of Korea SP / v.43, no.3, 2006 , pp. 92-99 More about this Journal
Abstract
In this paper, a low-power deblocking filter structure for H.264 video coding algorithm is proposed. By sharing addition hardware for common filter coefficients, we have designed an efficient deblocking filter structure. Proposed deblocking filter utilizes MUX and DEMUX circuits for input data sharing and shows 44.2% reduction for add operation. In the HDL coding simulation and FPGA implementation, we achieved 19.5% and 19.4% gate count reduction, respectively, comparison with the conventional deblocking filter structure. Due to its efficient processing scheme, the proposed structure can be widely used in H.264 encoding and decoding SoC.
Keywords
H.264; deblocking filter; blocking artifacts; boundary strength;
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