• JSTS:Journal of Semiconductor Technology and Science
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• v.10 no.3
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• pp.176- 184
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• 2010

A low-power inductorless 1:4 DEMUX and a 4:1 MUX for a 90 nm CMOS are presented. The DEMUX can be operated at a speed of 25 Gb/s with the power supply voltage of 1.05 V, and the power consumption is 8.9 mW. The area of the DEMUX core is $29\;{\times}\;40\;{\mu}m^2$. The operation speed of the 4:1 MUX is 13 Gb/s at a power supply voltage of 1.2 V, and the power consumption is 4 mW. The area of the MUX core is $30\;{\times}\;18\;{\mu}m^2$. The MUX/DEMUX mainly consists of differential pseudo-NMOS. In these MUX/DEMUX circuits, logic swing is nearly rail-to-rail, and a low $V_{dd}$. The component circuit is more scalable than a CML circuit, which is commonly used in a high-performance MUX/DEMUX. These MUX/DEMUX circuits are compatible with conventional CMOS logic circuit, and it can be directly connected to CMOS logic gates without logic level conversion. Furthermore, the circuits are useful for core-to-core interconnection in the system LSI or chip-to-chip communication within a multi-chip module, because of its low power, small footprint, and reasonable operation speed.

• Proceedings of the IEEK Conference
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• 1998.10a
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• pp.51-54
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• 1998

In this paper, we describe the design of the ATM Mux/Demux circuit between BSC and MSC for IMT-2000 Network. This ATM Mux/Demux circuit culd support 155Mbps optic interface with MSC. Using the CAM and DPRAM, this circuit performs ATM cell Mux/Demux functions in the BSC. MPC 860SAR processor was used for the signaling with MSC in this design.

• Proceedings of the IEEK Conference
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• 2001.06a
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• pp.237-240
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• 2001

Dense Wavelength division multiplexing(DWDM) lightwave system requires multiplexer, demultiplexer and optical filter. In this paper, thus, we propose the Add-Drop Mux/Demux based on a Mach-Zehnder interferometer(MZI) with fiber Bragg grating(FBG). The Add-Drop Mux/Demux using FBG and MZI is able to minimize system and reduce weight. We also analyze output characteristics of Add-Drop Mux/Demux and present the optimum design data through the computer simulation.

• Proceedings of the Korea Multimedia Society Conference
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• 2003.11b
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• pp.998-1001
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• 2003

DMB 단말 시스템에서는 Delivery Layer로 다중화 방식인 MPEG-2 TS 와 MPEG-4 System SL를 이용하도록 제안되었다. 본 논문에서는 DMB 단말 시스템에서 사용되는 MPEG 2 $\square$TS는 H/W로 구현하고 MPEG 4 System S/W로 구현하는데 있어서 효율적인 인터페이스를 제안한다.

• Proceedings of the IEEK Conference
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• 2003.11b
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• pp.251-254
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• 2003

DMB is a next-generation multimedia broadcasting system that not only enables digital broadcasting services such as transmission of CD-duality audio, traffic information, and real-time stock information, but also allows reception of high-quality digital TV in high-speed driving conditions. In the DMB system, MPEG-2 TS(Transport Stream) multiplex method and MPEG-4 System SL(Sync Layer) have been selected as the delivery layer. In this paper, an efficient interface scheme between an MPEG-2 TS processing hardware and software-implemented MPEG-4 system within a DMB terminal device is proposed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.51-58
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• 2002

In this paper, a 155/311 Mb/s MUX/DEMUX chip using ECL macrocell away has been developed with a single device. This device for a 2.5 Gb/s SDH based transmission system is to interleave the parallel data of 51 Mb/s into 155 Mb/s(or 311 Mb/s) serial data output, and is to interleave a serial input bit stream of 155 Mb/s(or 311 Mb/s) into the parallel output of 51 Mb/s. The input and output of the device ate TTL compatible at the low-speed end, but 100k ECL compatible at the high-speed end. The device has been fabricated with Motorola ETL3200 macrocell away The fabricated chip shows the typical phase margin of 180 degrees and output data skew less than 220ps at the high-speed end.

• Proceedings of the Korean Institute of Communication Sciences Conference
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• 1993.10a
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• pp.441-445
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• 1993

• Journal of Internet Computing and Services
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• v.2 no.1
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• pp.87-96
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• 2001

This article proposes traffic dispersion with optical transmission technical and development of transmission rate for the safe multicast computer communication in the high bandwidth, Recently multicast traffic such as distance conference or Internet broadcast increases therefore the importance of traffic dispersion and transmission rate is emphasized. Ultimately this article offers the way of carrying out the above suggestion, First this paper points out traffic problems occurred in voice and text centered transmission. Next, transmission rate can be controlled by optical transmission technic to solve above difficulties in the multimedia and Internet. We investigated the feature and output on Add-Drop Mux/Demux and Also presented charges of length accord each stage in interference. We can show, the best data of design as a result of this experiment.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.41 no.5
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• pp.27-36
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• 2004

In this paper, we propose the ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame multiplex/demultiplexer architecture for the edge switch system based on Linux that has 10 Gigabit Ethernet (10Gigabit Ethernet) port with 72Gbps capacities. we discuss the ethernet IPC with ethernet switch and we propose design and implementation of ethernet Inter-Processor Communication (IPC) network architecture and multiple gigabit ethernet frame rnultiplexing/demultiplexing scheme to handle 10gigabit ethernet frame instead of using 10gigabit network processor. And then ethernet Inter-Processor Communication (IPC) network architecture and 10gigabit ethernet frame MUX/DMUX architecture is designed verified and implemented.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2001.05a
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• pp.265-268
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• 2001

In this paper, we designed one-dimensional VLSI array with high speed processing in Fractal image compression. fractal image compression algorithm partitions the original image into domain blocks and range blocks then compresses data using the self similarity of blocks. The image is partitioned into domain block with 50% overlapping. Domain block is reduced by averaging the original image to size of range block. VLSI array is trying to search the best matching between a range block and a large amount of domain blocks. Adjacent domain blocks are overlapped, so we can improve of each block's processing speed using the reuse of the overlapped data. In our experiment, proposed VLSI array has about 25% speed up by adding the least register, MUX, and DEMUX to the PE.