• Journal of the Korea Institute of Information and Communication Engineering
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• v.25 no.12
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• pp.1914-1919
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• 2021

With the development of advanced industries, research on image processing hardware is essential, and timing verification at the gate level is required for actual chip operation. For FPGA-based verification, DDR3 memory interface was previously applied. But recently, as the FPGA specification has improved, DDR4 memory is used. In this case, when a previously used memory interface is applied, the timing mismatch of signals may occur and thus cannot be used. This is due to the difference in performance between CPU and memory. In this paper, the problem is solved through state optimization of the existing interface system FSM. In this process, data read speed is doubled through AXI Data Width modification. For actual case analysis, ZC706 using DDR3 memory and ZCU106 using DDR4 memory among Xilinx's SoC boards are used.

• Journal of IKEEE
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• v.21 no.4
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• pp.416-419
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• 2017

In this paper, we propose a new digital delay-locked loop (DLL) for high-speed DDR3/DDR4 SDRAMs. The proposed digital DLL adopts a fine delay line using phase interpolation to eliminate the jitter increase problem due to the boundary switching problem. In addition, the proposed digital DLL utilizes a new gradual search algorithm to eliminate the harmonic lock problem. The proposed digital DLL is designed with a 1.1 V, 38-nm CMOS DRAM process and has a frequency operating range of 0.25-2.0 GHz. It has a peak-to-peak jitter of 1.1 ps at 2.0 GHz and has a power consumption of about 13 mW.

• Journal of Radiation Industry
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• v.4 no.3
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• pp.289-295
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• 2010

The bacterium Deinococcus radiodurans is one of the most resistant organisms to the effects of ionizing radiation and other DNA-damaging agents. In this study, distributions of 10 ddr (DNA damage response) genes were investigated in 8 species of Deinococcus by polymerase chain reaction (PCR). We have compared the sequences of ddr genes of D. radiodurans, D. geothermalis and D. deserti, and selected primers which are suitable for the detection of ddr in different species of Deinococcus. A sequence homology search and PCR assay showed that ddrO, which encodes a global regulator of the radiation-desiccation response, was most well conserved in the Deinococcus lineage.

• Journal of the Korean Society of Radiology
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• v.1 no.1
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• pp.25-30
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• 2007

ROC(Receiver Operating Characteristic)curve is the method that estimate detected insignificant signal from the human's sense of sight, it has been raised excellent results. In this study, we evaluate image quality and equipment character by obtaining a chest image from CR(Computed Radiography) and DDR(Direct Digital radiography) using the human chest phantom, The parameter of exposure for obtaining chest image was 120 kVp/3.2 mAs and the SID(Source to Image Distance) was 180cm. The images were obtained by CR(AGFA MD 4.0 General plate, JAPAN) and DDR(HOLOGIC nDirect Ray, USA). Using some pieces of Aluminum and stone for expressing regions, then attached them on the heart, lung and thoracic vertebrae of the phantom. 29 persons hold radiology degrees were participated in ROC analysis. As a result of the ROC analysis, TPF(true positive fraction) and FPF(false positive fraction) of DDR and CR are 0.552 and 0.474 and 0.629 and 0.405, respectively. By using the results, the ROC curve of CR has higher image quality than DDR. According to the theory, DDR has the higher image quality than CR in chest X-ray image. But, CR has the higher image quality than DDR. quality of DDR inserted the enhance board. The results confirmed that image post-processing is important element decipherment of clinical.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.4
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• pp.45-50
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• 2012

A family of multi-die DRAM packages was developed that incorporate the full functionality of an SODIMM into a single package. Using a common ball assignment analogous to the edge connector of an SODIMM, a broad range of memory types and assembly structures are supported in this new package. In particular DDR3U, LPDDR3 and DDR4RS are all supported. The center-bonded DRAM use face-down wirebond assembly, while the peripherybonded LPDDR3 use the face-up configuration. Flip chip assembly as well as TSV stacked memory is also supported in this new technology. For the center-bonded devices (DDR3, DDR4 and LPDDR3 ${\times}16$ die) and for the face up wirebonded ${\times}32$ LPDDR3 devices, a simple manufacturing flow is used: all die are placed on the strip in a single machine insertion and are sourced from a single wafer. Wirebonding is also a single insertion operation: all die on a strip are wirebonded at the same time. Because the locations of the power signals is unchanged for these different types of memories, a single consolidated set of test hardware can be used for testing and burn-in for all three memory types.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.8
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• pp.136-142
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• 2013

CRC features have been added to increase the reliability of the data in memory products for high-speed operation, such as DDR4. High-speed memory products in a shortage of internal timing margin increases for the CRC calculation. Because the existing CRC requires many additional circuit area and delay time. In this paper, we show that the matrix-type CRC and a new XOR/XNOR gate could be improved the circuit area and delay time. Proposed matrix-type CRC can detect all odd-bit errors and can detect even number of bit errors, except for multiples of four bits. In addition, a single error in the error correction can reduce the burden of re-transmission of data between memory products and systems due to CRC errors. In addition, the additional circuit area, compared to existing methods can be improved by 57%. The proposed XOR gate which is consists of six transistors, it can reduce the area overhead of 35% compared to the existing CRC, 50% of the gate delay can be reduced.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2010.05a
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• pp.540-543
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• 2010

POWER PC series are common to the Central Processing Unit for Military Single Board Computer. Among them, G4 group, which contains the 74xx series supported by Freescale manufacturer is mainly used in the Military applications. We focus on the Interface between memory and controller. PCB stacking method, component routing, impedance matching and harsh environment for Military spec are the main constraints for implementation. Also, we developed memory as a module for the consideration of Military environments. The overall type of SBC should be designed by the form of 6U VME or 3U VME.

• Journal of KIISE
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• v.44 no.2
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• pp.124-131
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• 2017

The emerging next-generation manycore processors for high-performance computing are equipped with a high-bandwidth on-package memory along with the traditional host memory. The Multi-Channel DRAM (MCDRAM), for example, is the on-package memory of the Intel Xeon Phi Knights Landing (KNL) processor, and theoretically provides a four-times-higher bandwidth than the conventional DDR4 memory. In this paper, we suggest a mechanism to exploit MCDRAM for improving the performance of MPI intra-node communication. The experiment results show that the MPI intra-node communication performance can be improved by up to 272 % compared with the case where the DDR4 is utilized. Moreover, we analyze not only the performance impact of different MCDRAM-utilization mechanisms, but also that of core affinity for processes.

• Journal of Microbiology and Biotechnology
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• v.29 no.11
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• pp.1806-1816
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• 2019

Candida albicans is an opportunistic fungus possessing multiple virulence factors controlling pathogenicity. Cell wall proteins are the most important among these factors, being the first elements contacting the host. Ddr48 is a cell wall protein consisting of 212 amino acids. A DDR48 haploinsufficient mutant strain was previously found necessary for proper oxidative stress response and drug resistance. In this study, we aimed to further elucidate the role of Ddr48 by performing additional phenotypic characterization assays. A combinatory proteomic and bioinformatics approach was also undertaken to determine differentially expressed cell wall proteins. Results showed that the mutant strain exhibited a 10% decrease in adhesion mirrored by a 20% decrease in biofilm formation, and slight sensitivity to menadione, diamide, and SDS. Both strains showed similar hyphae formation, virulence, temperature tolerance, and calcofluor white and Congo red sensitivities. Furthermore, a total of 8 and 10 proteins were identified exclusively in the wild-type strain grown under filamentous and non-filamentous conditions respectively. Results included proteins responsible for superoxide stress resistance (Sod4 and Sod6), adhesion (Als3, Hyr4, Pmt1, and Utr2), biofilm formation (Hsp90, Ece1, Rim9, Ipp1, and Pra1) and cell wall integrity (Utr2 and Pga4). The lack of detection of these proteins in the mutant strain correlates with the observed phenotypes.

• Journal of Astronomy and Space Sciences
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• v.29 no.3
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• pp.315-320
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• 2012

We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 $MeVcm^2/mg$. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.