• Proceedings of the IEEK Conference
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• 1999.11a
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• pp.985-988
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• 1999

This paper describes the architecture and the IC implementation of a Direct Digital Frequency Synthesizer (DDFS). That is based on an angle rotation algorithm (CORDIC). It is shown that the architecture can be implemented as a multipliers, feedfoward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 0.35${\mu}{\textrm}{m}$ SAMSUNG KG90 Library.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.6 no.2
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• pp.126-137
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• 2007

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed. And we design the phase-to-sine converter using the phase accumulator of parallel type for generating the high frequency. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is saved by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is decreased according to the ROM size reduction.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.23 no.7
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• pp.1718-1731
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• 1998

Digital quadrature demodulator is needed for the coherent demodulation in the digital communication systems such as Binary Phase-Shift-Keying, Quadrature Phase-Shift-Keying, and Quadrature Anmplitude Modulation. Conventaionally, the DDFS (Direct Digital Frequency Synthsizer) is used for generating the carrier signal and seperate multi-pliers are used for mixing. And the DDFS is implemented using the ROM (Read Only Memory), which can be a bottle-neck neck when the fast-speed and small-area implementation is required. A new architecture is developed, which employs the circular rotation mode of the CORDIC algorithm for signal mixing as well as carrier generation. To optimize the hardware design parameters, the finiteword-length effects of the proposed implementation arachitecture are analyzed in comparison with a conventional ROM-based architecture. The hardware costs are also estimated, which showed that the proposed architecture occupies only a third of the area of the conventional ROM-based architecture for the same performance. A full-custom VLSI is developed using the proposed architecture.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.9
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• pp.48-53
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• 2007

Some digital signal processing applications, such as FFT, request multiplications with a group(or, groups) of a few predetermined coefficients. In this paper, based on the modified CSD algorithm, an efficient multiplier design method for predetermined coefficient groups is proposed. In the multiplier design for sine-cosine generator used in direct digital frequency synthesizer(DDFS), and in the multiplier design used in 128 point $radix-2^4$ FFT, it is shown that the area, power and delay time can be reduced up to 34%.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.9
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• pp.536-542
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• 2004

An architecture of direct digital frequency synthesizers (DDFS) is studied in this paper The Direct digital frequency synthesizers (DDFS) provide fast frequency switching with high spectral purity and are widely used in modern spread spectrum wireless communication systems. ROM-based DDFS uses a ROM lookup table to store the amplitude of a sine wave. In this paper, we suggest three new techniques to reduce the ROM size. One new technique uses more number of hierarchical levels in ROM structures. Another techniques use simple interpolation techniques combined with hierarchical ROM structures. A 12 bit sine wave is generated by using these techniques. Experimental results show that the new proposed techniques can reduce the required ROM size by up to 24%, when compared to that of a resent method[1].

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2009.10a
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• pp.401-404
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• 2009

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed. The new parallel ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is stored by the quantized-ROM and the differential ROM. To reduce the ROM size, we use the differential quantization technique with this two ROM. So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is affected mostly by this ROM reduction.

• IT SoC Magazine
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• s.3
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• pp.35-37
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• 2004

본 연구팀이 Hynix 0.35um CMOS 4M 2P 공정을 사용하여 제작한 민수용 DDFS (DAC를 포함한 single chip)는 DC부터 100MHz 까지 사용할 수 있으며(BW=100MHz) frequency 변환속도 약 30nS, 주파수해상도 0.0745Hz, 그리고 소비 전력은 120MHz 클럭에서 약 200mW이다. 본고에서는 언급하지 않았지만, 본 연구팀이 별도의 설계로 진행된 군수용 DDFS의 경우, 출력주파수는 DC부터 320MHz 까지 가능하고 소비 전력은 800MHz 클럭에서 약 400mW이다. 이처럼 DDFS는 특성 자체의 우수성 뿐 아니라, 각종 멀티미디어 기기 및 통신시스템의 급격한 디지털화 추세로 인해 주파수합성기도 디지털화 함으로써 VLSI화가 용이하고, 이에 따라 S/W에 의한 다기능화 (programmability), 응용성의 극대화, 및 저가격화를 추구할 수 있다는 점에서 주목해야 할 분야이다. 특히 반도체기술의 발전으로 지금까지 DDFS 구현의 가장 큰 장애로 대두되던 DAC의 고속화가 부분적으로 가능해지면서 (TTL-to-ECL interface 부가회로가 별도로 필요없이 직접적인 연결), DDFS의 시장 전망을 더욱 밝게 하고 있다.

• The Journal of the Acoustical Society of Korea
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• v.7 no.2
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• pp.51-64
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• 1988

The frequency synthesizer thar has very short transient time is the key to construct the Fast Frequency Hopping(FFH) system. A Direct Digital Frequency Synthesizer(DDFS) whose transient time is in the nS range has been implemented and the performance of which has been examined through this paper. And by considering the hopping characteristic it is confirmed that the DDFS is suitable for the FFH system. Finally an improvement method which can greatly enhances the SNR with the state-of-the-art techniques and simplifies the system design is presented.

• The Journal of the Acoustical Society of Korea
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• v.17 no.8
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• pp.103-109
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• 1998

디지털신호의 변조에는 기본적으로 진폭 편이 변조(ASK: Amplitude-Shift Keying), 주파수 편이 변조(FSK: Frequency-Shift Keying), 위상 편이 변조(PSK: Phase-Shift Keying) 등의 세 가지 방법이 있다. 본 논문에서는 표본클록 합성계수 방식에 관한 이론을 고찰하고, 클록초기치 누적방식의 DDFS를 이용하여 위에서 언급한 변조방법을 실현할 수 있는 주파수 도약 대역 확산 통신에 적합한 변조기를 구현하였다. 또한, 합성된 출력주파수 의 정현파형에 대한 스펙트럼 분석과 PN(Pseudo Noise) 부호를 사용한 순시적인 주파수 도 약 상태, 위상제어의 가능성 등을 확인한 결과 실험으로부터 다음과 같은 결과를 얻었다. 첫 째, 합성된 출력주파수는 주파수 Index에 따라 기준주파수에 정확히 정수배가 되며, 둘째, 합성된 정현파형의 스펙트럼으로 기본파와 여러 고조파의 크기를 비교하여 본 결과 50[dB] 이상의 차이가 남으로서 고조파 성분들이 상당히 감소되었음을 확인하였고, 셋째, PN 코드 를 사용하여 순시적인 주파수 도약 상태를 확인하여 본 결과 스위칭 시간이 빠르기 때문에 주파수 도약 특성이 뛰어남을 알 수 있었으며 또한, 누산기의 set/reset 상태를 변화시킴에 따라 위상이 제어됨을 입증하였다.

• Journal of the Institute of Convergence Signal Processing
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• v.8 no.3
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• pp.192-198
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• 2007

In this paper, a new method to reduce the size of ROM in the direct digital frequency synthesizer(DDFS) is proposed. The new ROM compression method can reduce the ROM size by using the two ROM. The quantized value of sine is stored by the quantized-ROM(Q-ROM) and the differential ROM(D-ROM). To reduce the ROM size, we use the differential quantization technique with this two ROM. First, we quantize the quarter sine wave with the $2^L$ address and store the quantized value at the Q-ROM. Second, after the $2^L$ address are equally divided into $2^M$ sampling intervals, the sampling value is quantized. And the D-ROM store only the difference between this quantized value and the Q-ROM. So the total size of the ROM in the proposed DDFS is significantly reduced compared to the original ROM. The ROM compression ratio of 67.5% is achieved by this method. Also, the power consumption is affected mostly by this ROM reduction.