• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.4
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• pp.86-90
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• 2007

An efficient sensing scheme applicable to DC-DC converters is proposed. The output voltage of the DC-DC converter is fed back and converted to a current signal at the input terminal of the sensor to decide if it is in the tolerable range. The comparison is accomplished by a current push-pull action. With the embedded reference current in the sensor realized from the reference voltage. The advantages of the scheme lie in the fairly accurate and efficient implementation in terms of power consumption and chip size overhead compared with conventional voltage-mode schemes as the major parameter in converting voltage to current is determined by (W/L) aspect ratio of the core transistors. In this paper, a DC-DC converter of 5V output from battery range of 2.2V${\sim}$3.6V adopting the proposed sensing scheme is implemented in a 0.35um CMOS process to prove the validity of the scheme.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.269-271
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• 2005

본 논문은 입력 필터 상호 작용 (Interacton)의 일반적인 해석 방법으로 입력 필터단이 연결된 전류 제어 DC-DC 변환기의 동특성을 해석한다. 또한 입력 필터단의 강한 영향을 받는 상태의 전류 제어 강압형 변환기의 새로운 소신호 해석 결과를 제시한다. 이론적 해석은 컴퓨터 시뮬레이션 결과 및 제작된 실험용 PWM DC-DC 변환기로 검증하였다.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.272-274
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• 2005

본 논문은 PWM DC-DC 변환기의 입력 임피던스를 Middlebrook의 EET (Extra Element Theorem)를 사용하여 해석할 수 있는 방법을 제시하고, 이를 이용하여 실제로 전압 제어, 전류 제어 승압형 변환기에 대한 입력 임피던스를 해석하였다. 유도된 수식은 간략화, 근사화를 통하여 보드 선도 (Bode plot)화 하였고, 입력 임피던스 특성 및 전류 루프, 피드백/피드포워드 루프, 전압루프의 영향을 해석하였다. 또한 이론적 해석은 컴퓨터시뮬레이션 결과 및 실제 제작된 PWM DC-DC 변환기의 실험 결과로 비교, 검증하였다.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.9
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• pp.1755-1762
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• 2016

In this paper, a small areal dual-output SC(switched capacitor) DC-DC converter with a improved range of an input voltage is presented. The conventional SC DC-DC converter has an advantage of low cost and small chip area. But, it has a narrow input voltage range to convert efficiently. Also, it has a lager chip area and a lower power efficiency from multiple outputs. The proposed SC DC-DC converter improves the power efficiency by using the capacitor array structure which efficiently converts the voltage according to the input voltage. By sharing two switch array, it reduces the number of switches and capacitors from 32 to 25. The proposed SC DC-DC converter was manufactured in a $0.18{\mu}m$ CMOS process. In the simulation, the range of the input voltage is 0.7~ 1.8V, the max. power efficiency is 90%, and the chip area is $0.255mm^2$.

• Journal of IKEEE
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• v.24 no.3
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• pp.853-858
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• 2020

This paper proposes a 2-ch DC-DC converter for OLED display with immunity against RF noise inserted from communication device. For RF signal immunity, an input voltage variation reduction circuit that attenuates as much as the input voltage variation is embedded. The boost converter for positive voltage V_POS operates in SPWM-PWM dual mode and has a dead time controller to increase power efficiency. The inverting charge pump for negative voltage V_NEG is a 2-phase scheme and operates in PFM using VCO to reduce output ripple voltage. Simulation results using 0.18 ㎛ BCDMOS process show that the overshoot and undershoot of the output voltage decrease from 10 mV to 2 mV and 5 mV, respectively. The 2-ch DC-DC converter has power efficiency of 39%~93%, and the power efficiency of the boost converter is up to 3% higher than the conventional method without dead time controller.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.2
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• pp.95-103
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• 2007

Dynamic voltage scaling (DVS) is a well-known and effective power management technique. While there has been research on slack distribution, voltage allocation and other aspects of DVS, its effects on non-voltage-scalable devices has hardly been considered. A DC-DC converter plays an important role in voltage generation and regulation in most embedded systems, and is an essential component in DVS-enabled systems that scale supply voltage dynamically. We introduce a power consumption model of DC-DC converters and analyze the energy consumption of the system including the DC-DC converter. We propose an energy-optimal off-line DVS scheduling algorithm for systems with DC-DC converters, and show experimentally that our algorithm outperforms existing DVS algorithms in terms of energy consumption.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.285-288
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• 2012

Since the non-overlapping gate driver used in conventional DC-DC boost converters generates fixed dead-times, the converters suffer from the body-diode conduction loss or the charge-sharing loss. To reduce the efficiency degradation due to these losses, this paper presents a PWM DC-DC boost converter with adaptive dead-time control. In light loads, power switching is also employed to increase the efficiency. The designed DC-DC boost converter can thus achieve high efficiency at wide current range. The proposed DC-DC boost converter has 3.3V output from a 2.5V input with 0.18um technology. It operates at 500KHz and has a maximum power efficiency of 97.8%.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.8
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• pp.805-808
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• 2011

This paper presents a design of high-efficiency and high-power class E power transmitter. The transmitter is composed of 300 Watt class E power amplifier and AC-DC converter. The AC-DC converter converts 220 V and 60 Hz AC to a 290 V DC. The generated DC voltage is directly applied to a bias of the class E power amplifier. Because the converter does not have DC-DC converter unit, it has very high conversion efficiency of about 98.03 %. To minimize the loss at the output of the power amplifier, high-Q inductor was implemented and deployed to the output resonant circuit. As a result, the 13.56 MHz class E power amplifier has a high power-added efficiency of 84.2 % at the peak output power of 323.6 W. The overall efficiency of class E power transmitter, including the AC-DC converter, is as high as 82.87 %.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.9 s.351
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• pp.23-30
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• 2006

This paper presents a design of a high-efficiency CMOS DC-DC boost converter using a current-sensing feedback method. High-precision current-sensing circuity is incorporated in order to sense the current flowing in the inductor, which determines the switching scheme of the pulse-width modulation. The external components or large chip area for the frequency compensation can be avoided while maintaining the stable operations of the converter. Various input/output voltage levels can be available through the external resistor strings. The designed DC-DC converter is fabricated in a 0.18-um CMOS technology with a thick-gate oxide option. The converter shows the maximum efficiency over 90% for the output voltage of 3.3V and load current larger than 200mA. The load regulation is 1.15% for the load current change of 100mA.

• Journal of IKEEE
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• v.15 no.2
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• pp.134-142
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• 2011

This paper describes a tripple-mode high-efficiency DC-DC buck converter. The DC-DC buck converter operate in PWM(Pulse Width Modulation) mode at moderate to heavy loads(100mA~500mA), in PFM(Pulse Frequency Modulation)at light loads(1mA~100mA), and in LDO(Low Drop Out) mode at the sleep mode(<1mA). In PFM mode DPSS(Dynamic Partial Shutdown Strategy) is also employed to increase the efficiency at light loads. The triple-mode converter can thus achieve high efficiencies over wide load current range. The proposed DC-DC converter is designed in a CMOS 0.18um technology. It has a maximum power efficiency of 96.4% and maximum output current of 500mA. The input and output voltages are 3.3V and 2.5V, respectively. The chip size is 1.15mm ${\times}$ 1.10mm including pads.