• Journal of Power Electronics
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• v.17 no.1
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• pp.222-231
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• 2017

In this paper, a new architecture for a cost-effective power conditioning systems (PCS) using a single-sourced asymmetric cascaded H-bridge multilevel inverter (MLI) for photovoltaic (PV) applications is proposed. The asymmetric MLI topology has a reduced number of parts compared to the symmetrical type for the same number of voltage level. However, the modulation index threshold related to the drop in the number of levels of the inverter output is higher than that of the symmetrical MLI. This problem results in a modulation index limitation which is relatively higher than that of the symmetrical MLI. Hence, an extra voltage pre-regulator becomes a necessary component in the PCS under a wide operating bias variation. In addition to pre-stage voltage regulation for the constant MLI dc-links, another auxiliary pre-regulator should provide isolation and voltage balance among the multiple H-bridge cells in the asymmetrical MLI as well as the symmetrical ones. The proposed PCS uses a single-ended DC-DC converter topology with a coupled inductor and charge-pump circuit to satisfy all of the aforementioned requirements. Since the proposed integrated-type voltage pre-regulator circuit uses only a single MOSFET switch and a single magnetic component, the size and cost of the PCS is an optimal trade-off. In addition, the voltage balance between the separate H-bridge cells is automatically maintained by the number of turns in the coupled inductor transformer regardless of the duty cycle, which eliminates the need for an extra voltage regulator for the auxiliary H-bridge in MLIs. The voltage balance is also maintained under the discontinuous conduction mode (DCM). Thus, the PCS is also operational during light load conditions. The proposed architecture can apply the module-integrated converter (MIC) concept to perform distributed MPPT. The proposed architecture is analyzed and verified for a 7-level asymmetric MLI, using simulation results and a hardware implementation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.12 no.1
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• pp.65-70
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• 2001

This paper presents a Receiver MMIC for the CDMA terminal. The complete circuit is composed of Low Noise Amplifier, Down Conversion Mixer, Intermediate Frequency Amplifier and Bias circuit. The Bias circuit implementation, which allows for compensation for threshold voltage and power supply voltage variation are provided. The proposed topology has high linearity and low noise characteristics. Results of the designed circuit are as follows: Overall conversion gain is 28.5 dB, input IP3 of LNA is 8 dBm, input IP3 of down conversion mixer is 0 dBm and total DC current consumption is 22.1 mA.

• Electrical & Electronic Materials
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• v.10 no.10
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• pp.1000-1004
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• 1997

In this paper the current-voltage characteristics of a submicron GaAs MESFET is simulated by using the self-consistent ensemble Monte Carlo method. The numerical algorithm employed in solving the two-dimensional Poisson equation is the successive over-relaxation(SOR) method. The total number of employed superparticles is about 1000 and the field adjusting time is 10fs. To obtain the steady-state results the simulation is performed for 10ps at each bias condition. The simulation results show the average electron velocity is modified by the gate voltage.

• Journal of the Korean Ceramic Society
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• v.45 no.1
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• pp.69-74
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• 2008

The effects of $SiO_2$ impurity on the high temperature resistivities of AIN ceramics have been investigated. When $SiO_2$ was added into 1 wt% $Y_2O_3$-doped AIN, DC resistivities have decreased and electrode polarizations disappeared. Impedance spectroscopy showed two semi-circles at $600^{\circ}C$, which were attributed to grain and grain boundary, respectively. $SiO_2$ doping had more significant effects on the grain resistivity than grain boundary resistivity, implying that doped Si acted as a donor in AIN lattice. In addition, voltage dependency of DC resistivity was observed, which might be related to dependency of size of grain boundary semi-circle on the bias voltage in impedance spectroscopy.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.28 no.6
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• pp.435-443
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• 2017

In this study, we analyzed the effects of the common-gate transistor bias of a switching mode CMOS power amplifier. Although the most earier works occured on the transistor sizes of the cascode structure, we showed that the gate bias of the common-gate transistor also influences the overall efficiency of the power amplifier. To investigate the effect of the gate bias, we analyzed the DC power consumption according to the gate bias and hence the efficiency of the power amplifier. From the analyzed results, the optimized gate bias for the maximum efficiency is lower than the supply voltage of the power amplifier. We also found that an excessively low gate bias may degrade the output power and efficiency owing to the effects of the on-resistance of the cascode structure. To verify the analyzed results, we designed a 1.9 GHz switching mode power amplifier using $0.18{\mu}m$ RF CMOS technology. As predicted in the analysis, the maximum efficiency is obtained at 2.5 V, while the supply voltage of power amplifier is 3.3 V. The measured maximum efficiency is 31.5 % with an output power of 29.1 dBm. From the measureed results, we successfully verified the analysis.

• Tribology and Lubricants
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• v.35 no.1
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• pp.1-8
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• 2019

Demand for plastic gears are increasing in many industries due to their low production cost, light weight, applicability without lubricant, corrosion resistance and high resilience. Despite these benefits, utilizing plastic gears is limited due to their poor material properties. In this work, DLC coating was applied to improve the tribological properties of polyamide66 gear. 0 V, 40 V, and 70 V of negative bias voltages were selected as a deposition parameter in DC magnetron sputtering system. Pin-on-disk experiment was performed in order to investigate the wear characteristics of the gears. The results of the pin-on-disk experiment showed that DLC coated polyamide66 with 40 V of negative bias voltage had the lowest friction coefficient value (0.134) and DLC coated PA66 with 0 V of negative bias voltage showed the best wear resistance ($9.83{\times}10^{-10}mm^3/N{\cdot}mm$) among all the specimens. Based on these results, durability tests were conducted for DLC coated polyamide66 gears with 0 V of negative bias voltage. The tests showed that the temperature of the uncoated polyamide66 gear increased to about $37^{\circ}C$ while the DLC coated gear saturated at about $25^{\circ}C$. Also, the power transmission efficiency of the DLC coated gear increased by about 6% compared to those without coating. Weight loss of the polyamide66 gears were reduced by about 73%.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2000.05b
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• pp.142-145
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• 2000

The performance of ac plasma display panels (PDP) is influenced strongly by the surface glow discharge characteristics on the MgO thin films. This paper deals with the surface glow discharge characteristics and some physical properties of MgO thin films prepared by reactive RF planar unbalanced magnetron sputtering in connection with ac PDP. The samples prepared with the dc bias voltage of -10V showed lower discharge voltage and lower erosion rate by ion bombardment than those samples prepared by conventional magnetron sputtering or E-beam evaporation. The main factor that improves the discharge characteristics by bias voltage is considered to be due to the morphology changes or crystal structure of the MgO thin film by ion bombardment during deposition process.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1572-1575
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• 1996

A new type $Cu_{x}N/Cu/Cu_{x}N$ thin film electrode material with high adhesion to glass was developed by the dc reactive planar magnetron sputtering system for the PDP(Plasma Display Panel). The adhesive force of the $Cu_{x}N$ thin film was in the range of $20{\sim}40(N)$ under the conditions of the $N_2$ partial pressure of 15%, discharge current of 70mA, discharge voltage of 450V and substrate bias voltage of -100V. The adhesive force was depended on the $N_2$ partial pressure, discharge current and substrate bias voltage.

• Journal of the Korean Vacuum Society
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• v.21 no.6
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• pp.322-327
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• 2012

The strain effects of ZnSe epilayer on ZnSe/GaAs heterojunction structure grown by molecular beam epitaxy have been investigated by using electroreflectance (ER) spectroscopy. The ER measurements were performed as a function of modulation voltage, dc bias voltage, and temperature. From the room temperature ER spectrum, we observed a heavy-hole (HH: 2.609 eV) and light-hole (LH: 2.628 eV) transitions due to a compressive strain. With increasing the bias voltage, the amplitude of HH transition signal decreased and the amplitude of LH transition signal was almost the same. From the temperature dependence of ER spectra, we have studied the interaction between the strain and the thermal expansion coefficient.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1968-1970
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• 1996

We investigate a surface-micromachined polysilicon microgyroscope, whose resonant frequencies are electrostatically-tunable after fabrication. The microgyroscope with two oscillation nudes has been designed so that the resonant frequency in the sensing mode is higher than that in the actuating mode. The microgyroscope has been fabricated by a 4-mask surface-micrormachining process, including the deep RIE of a $6{\mu}m$-thick LPCVD polycrystalline silicon layer. The resonant frequency in the sensing mode has been lowered to that in actuating mode through the adjustment of an inter-plate bias voltage; thereby achieving a frequency matching at 5.8kHz under the bias voltage of 2V in a reduced pressure of 0.1torr. For an input angular rate of $50^{\circ}/sec$, an output signal of 20mV has been measured from the tuned microgyroscope under an AC drive voltage of 2V with a DC bias voltage of 3V.