• Journal of the Korean Institute of Telematics and Electronics B
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• 제30B권2호
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• pp.33-43
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• 1993

Lock mechanism is essential for synchronization on the multiprocessor systems. Lock mechanism needs to reduce the time for lock operation in low lock contention. Lock mechanism must consider the case of the high lock contention. The conventional lock control scheme in memory results in the increase of bus traffic and memory utilization in lock operation. This paper suggests a lock scheme which stores the lock data in cache and manages it efficiently to reduce the time spent in lock operation when the lock contention is low on a multiprocessor system built on HiPi-bus(Highly Pipelined bus). This paper also presents the design of the HIPi-CLOCK (Highly Pipelined bus Cache LOCK mechanism) which transfere the data from on cache to another when the lock contention is high. The designed simulator compares the conventional lock scheme which controls the lock in memory with the suggested HiPi-CLOCK scheme in terms of the RMW(Read-Modify-Write) operation time using simulated trace. It is shown that the suggested lock control scheme performance is over twice than that of the conventional method in low lock contention. When the lock contention is high, the performance of the suggested scheme increases as the number of the shared lock data increases.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• 제22권3호
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• pp.131-146
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• 2023

Smart card data is widely used in the public transportation field. Despite the inevitability of various errors occur during the data collection and storage; however, smart card data errors have not been extensively studied. This paper investigates inherent errors in boarding and alighting station information in smart card data. A comparison smart card data and bus boarding and alighting survey data for the same time frame shows that boarding station names differ by 6.2% between the two data sets. This indicates that the error rate of smart card data is 6.2% in terms of boarding station information, given that bus boarding and alighting survey data can be considered as ground truth. This paper propose 6-step algorithm for correcting errors in smart card boarding station information, linking them to corresponding information in Bus Information System(BIS) Data. Comparing BIS data and bus boarding and alighting survey data for the same time frame reveals that boarding station names correspond by 98.3% between the two data sets, indicating that BIS data can be used as reliable reference for ground truth. To evaluate its performance, applying the 6-step algorithm proposed in this paper to smart card data set shows that the error rate of boarding station information is reduced from 6.2% to 1.0%, resulting in a 5.2%p improvement in the accuracy of smart card data. It is expected that the proposed algorithm will enhance the process of adjusting bus routes and making decisions related to public transportation infrastructure investments.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제42권4호
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• pp.9-18
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• 2005

This paper proposes the novel synchronous segmented bus architecture that has the pipeline bus architecture based on OCP(open core protocol) and the memory-oriented bus for MPEG system. The proposed architecture has bus architectures that support the memory interface for image data processing of MPEG system. Also it has the segmented hi-directional multiple bus architecture for multitasking processing by using multi -masters/multi - slave. In the scheme address of masters and slaves are fixed so that they are arranged for the location of IP cores according to operational characteristics of the system for efficient data processing. Also the bus architecture adopts synchronous segmented bus architecture for reuse of IP's and architecture or developed chips. This feature is suitable to the high performance and low power multimedia SoC systum by inherent characteristics of multitasking operation and segmented bus. Proposed bus architecture can have up to 3.7 times improvement in the effective bandwidth md up to 4 times reduction in the communication latency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• 제46권2호
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• pp.38-44
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• 2009

Bus system consists of several masters, slaves, arbiter and decoder in a bus. Master means the processor that performs data command like CPU, DMA, DSP and slave means the memory that responds the data command like SRAM, SDRAM and register. Furthermore, as multiple masters can't use a bus concurrently, arbiter plays an role in bus arbitration. In compliance with the selection of arbitration method bus system performance can be charged definitely. Fixed priority and round-robin are used in general arbitration method and TDMA and Lottery bus methods are proposed currently as the improved arbitration schemes. In this stuff, we proposed the score arbitration method and composed TLM algorithm. Also we analyze the performance compared with general arbitration methods through simulation. In the future, bus arbitration policy will be developed with the basis of the score arbitration method and improve the performance of bus system.

• Journal of KIISE:Computer Systems and Theory
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• 제32권6호
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• pp.324-332
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• 2005

In general, bus system consumes a very significant portion of power in a chip. Bus splitting can be used to reduce the energy dissipation and to reduce the Propagation delay on the bus by lowering the parasitic load of each bus segment. Data exchange probability distribution between a set of interconnected processing elements affects the average energy dissipation of the splitted bus architectures. In this research, we have developed tree-based bus splitting techniques and design methodologies, as an extension of horizontally aligned bus splitting. We have developed the methodology to select near-optimal bus architectures for low energy dissipation when data exchange probability distribution of a system is given. Experimental results show that the proposed techniques can reduce energy dissipation on the bus by up to 83$\%$.

• International Journal of Highway Engineering
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• 제18권5호
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• pp.105-115
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• 2016

PURPOSES : This study was initiated to analyze the characteristics of bus traffic accidents, by bus types, using the decision tree in order to establish customized safety alternatives by bus types, including the intra-city bus, rural area bus, and inter-city bus. METHODS : In this study, the major elements involved in bus traffic accidents were identified using decision trees and CHAID algorithm. The decision tree was used to identify the characteristics of major elements influencing bus traffic accidents. In addition, the CHAID algorithm was applied to branch the decision trees. RESULTS : The number of casualties and severe injuries are high in bus accidents involving pedestrians, bicycles, motorcycles, etc. In the case of light injury caused by bus accidents, different results are found. In the case of intra-city bus accidents, the probability of light injury is of 77.2% when boarding a non-owned car and breaching of duty to drive safely are involved. In the case of rural area bus accidents, the elements showing the highest probability of light injury are boarding an owned car, vehicle-to-vehicle accidents, and breaching of duty to drive safely. In the case of intra-city bus accidents, boarding owned car, streets, and vehicle-to-vehicle accidents work as the critical elements. CONCLUSIONS : In this study, the bus accident data were categorized by bus types, and then the influential elements were identified using decision trees. As a result, the characteristics of bus accidents were found to be different depending on bus types. The findings in this study are expected to be utilized in establishing effective alternatives to reduce bus accidents.

• 한국ITS학회:학술대회논문집
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• 한국ITS학회 2006년도 제5회 추계학술대회 및 정기총회
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• pp.166-170
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• 2006

• The Transactions of the Korean Institute of Electrical Engineers D
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• 제49권12호
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• pp.675-682
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• 2000

When a system is composed of multi-boards, an efficient bus arbitration method for the data transfer bus must be provided for guaranteeing proper operations. In this paper, a new test methodology is developed which is used for testing on-line bus arbitration. In the new test methodology, events that are occurred during bus arbitration are defined, and expected signals during fault-free bus arbitration are compared with the signals captured during on-line bus arbitration using boundary-scan cells. For this, a new test architecture is proposed which is efficient for the maintenance and the repair of multi-board systems. In addition, the new methodology can be used with off-line interconnect test using boundary-scan.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 한국정보통신학회 2013년도 춘계학술대회
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• pp.345-348
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• 2013

This paper provides a method for compression and transmission of on-chip bus data. As the data traffic on on-chip buses is rapidly increasing with enlarged video resolutions, many video processor chips suffer from a lack of bus bandwidth and their IP cores have to wait for a longer time to get a bus grant. In multimedia data such as images and video, the adjacent data signals very often have little or no difference between them. Taking advantage of this point, this paper develops a simple bus data compression method to improve the chip performance and presents its hardware implementation. The method is applied to a Video Codec - 1 (VC-1) decoder chip and reduces the processing time of one macro-block by 13.6% and 10.3% for SD and HD videos, respectively.

• Journal of IKEEE
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• 제28권1호
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• pp.116-122
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• 2024

AMBA AHB-Lite bus is widely used in on-chip bus protocol for low-power and cost-effective SoC. However, it lacks built-in error detection and correction for end-to-end data integrity. This can lead to data corruption and system instability, particularly in harsh environments like automotive applications. To mitigate this problem, this paper proposes the application of SEC-DED (Single Error Correction-Double Error Detection) to AMBA AHB-Lite bus. It aims not only to detect errors in real-time but also to correct them, thereby enhancing end-to-end data integrity. Simulation results demonstrate real-time error detection and correction when errors occur, which bolsters end-to-end data integrity of automotive on-chip bus.