• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2621-2624
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• 2003

In this paper, we designed 12Bit DAC(Digital to Analog Converter) that applied to multiple-valued logic system to Binary system. The proposed D/A Converter structure consists of the Binary to Quaternary Converter(BQC) and Quaternary to Analog Converter(QAC). The BQC converts the two input binary signals to the one Digit Quaternary output signal. The QAC converts the Quaternary input signal to the Analog output signal. The proposed DAC structure can implement voltage mode DAC that high resolution low power consumption with reduced chip area. And also, it has advantage of the easy expansion of resolution and fast settling time.

• Proceedings of the KIEE Conference
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• 2009.07a
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• pp.1960_1961
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• 2009

본 논문에서는 PID, PWM, HSC, 컴퓨터와의 호스트 통신, 외부 DAC 인터페이스를 FPGA만을 이용하여 하나의 Chip에 구현하고 DC 서보 모터의 속도를 설정한 제어 상태로 안정화시킬 수 있는 시스템을 구현하고자 한다. 컴퓨터에서 설정한 설정치(SV)와 P, I, D의 이득 값을 호스트 통신으로 데이터 블록은 해당 블록으로 전달하며 DC 서보 모터의 엔코더에서 나오는 $90^{\circ}$ 위상차가 있는 2채널의 펄스는 HSC 블록을 거쳐 프로세스치(PV)를 생성 고 이로부터 얻어진 SV와 PV의 편차(E)를 산출한 후 PID 제어 동작을 수행한다. 그 결과인 조작치(MV)를 PWM 블록에 제공하여 실질적으로 DC 서보 모터를 구동하는 H-bridge 회로를 구동한다. 또한 FPGA 내부의 SV, PV, E, MV를 오실로스코프로 계측하기 위해 DAC 인터페이스 블록을 첨가 하여 외부 디지털 아날로그 변환기(DAC)를 제어 하였다.

• 한국정보디스플레이학회:학술대회논문집
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• 2008.10a
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• pp.696-699
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• 2008

A 10-bit source driver using low temperature poly-silicon(LTPS) TFTs is developed. To reduce the DAC area, the DAC structure including two 5-bit resistor-string DACs and analog buffer, which has analog adder is proposed. The source driver is fabricated using LTPS process and its one channel area is $3,200{\mu}m\;{\times}\;260{\mu}m$. The simulated INL and DNL of output voltages are less than 3 LSB and 1 LSB, respectively.

• Proceedings of the IEEK Conference
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• 2009.05a
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• pp.313-315
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• 2009

In this thesis, A methodology of system implement for PID controller, PWM logic, HSC logic, Host Communication and external DAC interface are implemented into single FPGA chip is proposed. The implemented system is used to control the speed of DC servo motor. A DATA block transfers set point value(SV) and P, I, D gain parameters to the corresponding Blocks respectively by the Host Communication to Computer. A HSC block generates process value(PV) by a pulse and $90^{\circ}$ shifted pulse from the encoder A PID block makes error(E) signal from the set value and process value and output manufacture value(MV) through the PID controller. In PWM block using the MV from the PID block, drives H-bridge controlling the Motor. Also DAC interface controls the DAC to graph the digital signal such as SV, PV, E, MV in FPGA onto the Oscilloscope.

• Proceedings of the SOHE Conference
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• 1997.12a
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• pp.33-37
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• 1997

Cotton fabric was treated with chitosan solution by pad-dry(-cure) method to impart antimicrobial properties. Four chitosans of different degree of deacetylation(DAC: 65~95％) with similar molecular weight(ca. 50, 000) and one chitosan oligomer(MW 1, 800, DAC 86％) were used. Antimicribial activity against Staphylococcus aureus was evaluated by the Shake Flask Method. Treated fabrics were laundered up to 20 times according to AATCC Test Method 60-1986 and antimicrobial activity of laundered fabrics was evaluated. The antimicrobial activity was increased with the concentration and DAC of chitosan used. And the cured samples showed better durability to laundering than not-cured samples. Crosslinker and binder decreased the antimicrobial activity of fabrics treated with chitosan oligomer and were not effective to improve the durability to washing.

• Journal of the Korean Institute of Telematics and Electronics S
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• v.36S no.5
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• pp.122-131
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• 1999

저주파의 아날로그 신호를 디지털 신호로 변환하기 위해 sigma-delta 아날로그-디지털 변환기의 이용이 용이하다. 이 변환기는 변조기와 디지털 필터로 구성되는데 본 논문에서는 변조기에 대해서만 언급한다. 모델링을 통해 14비트 분해능을 갖는 2차 sigma-delta 변조기를 설계하기 위한 변조기의 구성요소 즉 연산 증폭기, 적분기, 내부 ADC 및 DAC의 최대 허용 에러 범위를 규정하였으며, 이를 토대로 연산증폭기, 2비트 ADC 및 DAC 등을 설계·검증하고, 이들을 서로 연결하여 2차 sigma-delta 변조기를 구성하였다. 3비트 ADC의 기준전압을 조절하여 변조기 성능 향상을 도모하였으며, 내부 DAC를 축전기 및 간단한 제어회로로 구성하여 비선형성 에러를 최소화하였다. 설계된 각각의 구성요소들은 모델링에서 정의된 에러 범위를 모두 만족하였으며, 전체 변조기는87㏈의 입력범위와 87㏈의 최대 신호 대 잡음 비를 가졌다.

• Proceedings of the IEEK Conference
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• 2003.11c
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• pp.216-219
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• 2003

In this paper, we present performance analysis of an IEEE P802.15.3a high rate wireless personal area network transceiver. This physical layer standard uses QOSK as its sub-channel modulation scheme and orthogonal frequency domain modulation (OFDM) for sub-bands. OFDM is used for each sub-band so that multi-path effects are absorbed by equalizer and guard, and fading can be approximately modeled as additive white Gaussian noise. In multi-band ultra-wideband system, DAC quantization error is important noise source since high resolution conversion cannot be used due to high power consumption. Simulation result shows that, to get 640-Mbps throughput, at least 5-bits precision is necessary to maintain bit-error rate under 10$\^$-2/, which can be lowered, with channel coding, to 10$\^$-6/ that is the bit-error rate required by IEEE 802.15 upper protocol layer, in 4-meter LOS fading channel.

• JSTS:Journal of Semiconductor Technology and Science
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• v.11 no.1
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• pp.23-32
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• 2011

A 40 fJ/c-s, 1 V, 10-bit SAR ADC is presented for energy constrained wearable body sensor network application. The proposed 10-bit dual sampling capacitive DAC topology reduces switching energy by 62% compared with 10-bit conventional SAR ADC. Also, it is more robust to capacitor mismatch than the conventional architecture due to its cancelling effect of each capacitive DAC. The proposed SAR ADC is fabricated in 0.18 ${\mu}m$ 1P6M CMOS technology and occupies 1.17 $mm^2$ including pads. It dissipates only 1.1 ${\mu}W$ with 1 V supply voltage while operating at 100 kS/s.

• Proceedings of the Korean Society of Propulsion Engineers Conference
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• 2017.05a
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• pp.353-357
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• 2017

The research trends and major technologies of the divert attitude control system(DACS), which is the core of the anti-missile system, are described. The operating concept and characteristics according to the fuel used are summarized. The characteristics of typical weapon system applying solid(SM3 Block IB/IIA) and liquid(THAAD) fuels were discussed. In the future, it will be necessary to study various types of DACS in the strategic concept of the defense weapon system.

• Journal of Mechanical Science and Technology
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• v.20 no.6
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• pp.840-848
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• 2006

We carried out numerical studies to investigate the single- and two-phase flow characteristics in the single- and multi-channels. We used the finite volume method to solve the mass and momentum conservation equations. The volume of fluid model is used to predict the two-phase flow in the channel. We obtained the distribution of velocity fields, pressure drop and air volume fraction for different water mass flow rates. We also calculated the distribution of mass flow rates in the multi-channels to understand how the flow is distributed in the channels. The calculated results for the single- and two-phase flow are partly compared with the present experimental data both qualitatively and quantitatively, showing relatively good agreement between them. The numerical scheme used in this study predicts well the characteristics of single-and two-phase flow in a multi-channel.