• Electrical & Electronic Materials
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• v.9 no.8
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• pp.813-818
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• 1996

Amorphous As$_{10}$Ge$_{15}$ Te$_{75}$ device shows the memory switching characteristics under d.c. bias. In bulk material, a-As$_{10}$Ge$_{15}$ Te$_{75}$ switching threshold voltage (V$_{th}$) is very high (above 100 volts), but in the case of thin film, V$_{th}$ decreases to a few or ten a few volts. The characteristics of V$_{th}$ depends on the physical dimensions such as the thickness of thin film and the separation between d.c. electrodes, and the annealing conditions. The switching threshold voltage decreases exponentially with increasing annealing temperature and annealing time, but increases linearly with the thickness of thin film and exponentially with increasing the separation between d.c. electrodes. The desirable low switching threshold voltage, therefore, can be obtained by the stabilization through annealing and changing physical dimensions.imensions.sions.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1995.11a
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• pp.67-70
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• 1995

Amorpous As$\sub$10/Ge$\sub$15/Te$\sub$75/ device shows the memory switching characterisite under d.c. bias. In bulk material, a-As$\sub$10/Ge/sub15/Te$\sub$75/s switching voltage range is above 100 volts. Our purposes in this gaudy are decreasing a switching threshold voltage, finding the properties of d.c., a.c. conduction, and the characterisitics of switching threshold voltage fur a-As$\sub$10/Ge$\sub$15/Te$\sub$75/. As the results, the d.c.and a.c. conductivities increase with temperature. From the data of conductivity, various electrical and physical properties are obtained experimentally. The switching threshold voltages decrease with increasing annealing temperature and time, but increase with increasing film thickness and distance of electrode for d.c. bias.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.37 no.6
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• pp.24-33
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• 2000

Switching behaviour of the ferroelectric thin film and device characteristics of the MFSFET(Metal-Ferroelectric-Semiconductor FET) are simulated with taking into account the accumulation of oxygen vacancies near interface between the ferroelectric thin film and the bottom electrode caused by the progress of fatigue. In our switching model, relative switched charge is 0.74 nC before fatigue, but after the progress of fatigue it reduces to 0.15 nC with the generation of oxygen vacancies. It indicates that the generation of oxygen vacancies strongly suppresses polarization reversal. $C-V_G\;and\;I_D-V_G$ curves in our MFSFET device model exhibit the memory window of 2 V and show the accumulation, the depletion and the inversion regions in capacitance characteristic clearly. The difference of saturation drain current of the device before fatigue in shown by the dual threshold voltages in $I_D-V_G$ curve as 6nA/$cm^2$ and decreases as much as 50% after fatigue. Decrease of the difference of saturation drain currents by fatigue implies that the accumulation of oxygen vacancies with the fatigue should be avoided in the device application. Our simulation model is expected to play an important role in estimation of the behavior of MFSFET device with various ferroelectric thin films.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.384-384
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• 2012

PRAM switching device by using current pulse modulation was investigated to verify its possibility for 3D architecture. In this work, two phase change materials connected in series having a different crystallization temperature are used. Its structural for different phase change material was evaluated by electrical resistance. We confirmed that Germanium-Antimony-Tellurium (GST) alloy and Germanium- Copper-Tellurium (GCT) alloy material were selected according to crystallization temperature, ${\sim}180^{\circ}C$ for switching and ${\sim}240^{\circ}C$ for memory devices, respectively. From this research, it is expected that phase change switching device could have advantages of process in terms of material similarity and structural simplification.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.36D no.11
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• pp.63-70
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• 1999

A PLT(10) thin film has been deposited on $Pt/TiO_2/SiO_2/Si$ substrate by sol-gel method, and its switching characteristics have been investigated with various top electrode areas, input pulse voltages and loan resistances. As the external input pulse voltage increases from 2V to 5V, the switching time decreases from $0.49{\mu}s$ to $0.12{\mu}s$. The activation energy ($E_a$) obtained from the relations between the switching time and the applied pulse voltage is evaluated as 209kV/cm. The switched charge densities at 5V obtained from the hysteresis loop and the polarization switching are $11.69{\mu}C/cm^2$ and $13.02{\mu}C/cm^2$, respectively, which agree relatively well with each other and show the difference of 10%. When the top electrode area increases from TEX>$3.14{\times}10^{-4}cm^2$ to $5.03{\times}10^{-3}cm^2$ and the load resistance increases from 50${\Omega}$ to 3.3$k{\Omega}$, the switching time increases from $0.12{\mu}s$ to $1.88{\mu}s$ and from $0.12{\mu}s$ to $9.7{\mu}s$, respectively. These switching characteristics indicate that PLT(10) thin film can be well applied in nonvolatile memory devices.

• The Transactions of the Korean Institute of Electrical Engineers
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• v.44 no.7
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• pp.901-907
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• 1995

The switching characteristics of As$_{10}$ Ge$_{15}$ Te$_{75}$ thin film were investigated under d.c. bias. And the frequency dependence of the conductivity was analysed with regard to the temperature dependence, in order to find the physical properties of the As$_{10}$ Ge$_{15}$ Te$_{75}$ thin film ; a characteristic relaxation time (.tau.$_{0}$ ), the spatial density of defect states (N), and the localized wavefunction (.alpha.$^{-1}$ ). It was formed that the threshold voltage depends on thickness, electrode distance, annealing time and temperature, respectively. The threshold voltage is increased as the thickness and the electrode distance is increased, while the threshold voltage is decreased in proportion to the increased annealing time and temperature.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• Proceedings of the Korean Magnestics Society Conference
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• 2004.06a
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• pp.12-12
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• 2004

• Journal of the Korean Magnetics Society
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• v.19 no.1
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• pp.22-27
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• 2009

Reduction of the critical current density ($J_c$) for STT magnetization switching is most important issue of magnetic tunnel junctions (MTJs) based MRAM. This report describes how to decrease the Jc and will introduce the recent research progresses of STT-MRAM devices with material engineering and structural improvement, respectively.

• Proceedings of the Korean Magnestics Society Conference
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• 2000.09a
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• pp.5-32
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• 2000

MRAM, High performance MRAM using MTJS demostrated, fully integrated MTJ MRAM with CMOS circuits, write time ~2.3 nsec; read time ~3 nsec, Thermally stable up to ~350 C, Switching field distibution controlled by size & shape. Magnetic Tunnel Junction Properties, Magnetoresistance: ~50% at room temperature, enhanced by thermal treatment, Negative and Positive MR by interface modification, Spin Polarization: >55% at 0.25K, Insensitive ot FM composition, Resistance $\times$ Area product, ranging from ~20 to 10$^{9}$ $\Omega$(${\mu}{\textrm}{m}$)$^{2}$, Spin valve transistor, Tunnel injected spin polarization for "hot" electrons, Decrease of MTJMR at high bias originates from anode.