• 대한전자공학회논문지SD
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• 제39권7호
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• pp.57-65
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• 2002

본 논문에서는 CMOS로 구현된 2.5v 10-bit 300MSPS의 D/A 변환기를 제안하였다. 이를 위해 전체구조는 고속동작에 유리한 전류구동 방식의 8+2 분할 타입으로 상위 8-bit은 Thermometer Code 기법을 이용한 전류셀 매트릭스(Current Cell Matrix)로, 하위 2-bit은 이진 가중 전류열(Binary Weighted Current Array)로 설계하였다. 우수한 다이내믹 특성 및 고속 동작을 만족시키기 위해 낮은 글리치 에너지를 갖는 새로운 전류셀과 BDD(Binary Decision Diagram)에 의한 논리합성 기법을 활용한 새로운 역 Thermometer Decoder를 제안하였다. 제안된 DAC는 $0.25{\mu}m$, 1-Poly, 5-Metal, n-well CMOS 공정으로 제작되었으며, 유효 칩 면적은 $1.56mm^2$이고, 2.5V의 전원전압에서 84mW의 전력소모를 나타내었다. 모의실험 및 측정을 통해 최대 글리치 에너지는 0.9pVsec@fs=100MHz, 15pVsec@fs=300MHz로 나타났다. 또한 출력 주파수가 1MHz, 샘플링 주파수가 300MHz에서의 INL과 DNL은 약 ${\pm}$1.5LSB 이내로, SFDR은 45dB로 측정되었다.

• 전자공학회논문지
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• 제49권11호
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• pp.149-156
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• 2012

디지털 입력 D급 증폭기는 보청기에서 사용되고 있으며 D급 증폭기는 디지털 회로와 아날로그 회로로 구성되어진다. 아날로그 회로는 가청 주파수 대역에서 잡음을 억제하고 디지털 입력을 아날로그 신호로 변환한다. 본 논문에서 제안한 인터폴레이티드 디지털 델타-시그마 변조기는 디지털 신호 처리기의 출력 신호를 D/A 변조기 입력에 적합하도록 데이터를 변조시킨다. 디지털 필터는 16-bit, 25-kbps 펄스 코드 변조 신호를 16-bit, 50-kbps 신호로 보간 작업을 한다. 이 보간 필터 출력은 3차 디지털 델타-시그마 변조기를 통하여 노이즈 쉐이핑(noise shaping) 처리된다. 최종적으로, 1.5-bit, 3.2-Mbps 신호가 D/A 변조기 입력으로 인가된다.

• 대한전자공학회논문지SD
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• 제48권4호
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• pp.14-23
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• 2011

본 논문에서는 자체보정 벡터 발생기(Self-Calibrated Vector Generator)를 이용한 7-bit 2GSPS folding/interpolation A/D Converter (ADC)를 제안한다. 제안하는 ADC는 2GSPS 의 고속 변환에 적합한 상위 2-bit, 하위 5-bit 인 분할구조로 설계 되었으며, 각각의 folding/interpolation rate는 4와 8로 설정되었다. 최대 1GHz의 높은 입력신호를 처리하기 위해 cascade 구조의 preprocessing block을 적용하였으며, 전압 구동 방식 interpolation 기법을 적용하여 기준전압 생성 시 발생하는 추가적인 전력소모를 최소화하였다. 또한, 새로운 개념의 자체보정 벡터 발생기를 이용하여 device mismatch, 기생 저항 및 커패시턴스 등에 의한 offset error를 최소화하였다. 제안하는 ADC는 1.2V 0.13um 1-poly 7-metal CMOS 공정을 사용하여 설계 되었으며 calibration 회로를 포함한 유효 칩 면적은 2.5$mm^2$ 이다. 측정 결과 입력 주파수 9MHz, sampling 주파수 2GHz에서 39.49dB의 SNDR 특성을 보이며, calibration 회로의 작동결과 약 3dB 정도의 SNDR의 상승을 확인하였다.

• Journal of information and communication convergence engineering
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• 제5권2호
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• pp.112-115
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• 2007

A CMOS TDC(time-to-digital converter) is proposed which has a simple cyclic structure. The proposed TDC consists of pulse-shrinking elements, D latches and D flip-flops. The operation is based on pulse-shrinking of the input pulse. The resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements, D latches and D flip flops. The TDC performance is improved in viewpoints of power consumption and chip area. Simulation results are shown to illustrate the performance of the proposed TDC circuit.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2014년도 추계학술대회 논문집
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• pp.159-160
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• 2014

본 논문에서는 ${\Delta}$결선으로 구성된 Modular Multilevel Converter(MMC)에서 흐르는 전류가 매우 적은 경우 계통에 영향이 없이 셀 직류전압의 불평형을 제어할 수 있도록 영상분전류를 주입하는 방법을 제안하였고, 시뮬레이션을 통해 검증하였다.

• 전력전자학회논문지
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• 제18권1호
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• pp.91-102
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• 2013

This paper proposes the improved LCCT(Inductor-Capacitor-Capacitor-Trans) Z-source DC-DC converter (Improved LCCT ZSDC) which can generate the bipolar output voltages according to duty ratio D. The proposed converter has the characteristic and structure of Quasi Z-source DC-DC converter(Quasi ZSDC) and conventional LCCT Z-source DC-DC converter(LCCT ZSDC). To confirm the validity of the proposed method, PSIM simulation and a DSP based experiment were performed for each converter. In case which the input DC voltage is 70V, the bipolar output DC voltage of positive 90V and negative 50V could generate. Also, as comparison result of the capacitor voltage ripple in Z-network and the input current under the same condition for each converter, the voltage stress and the capacitor voltage in Z-network of the proposed method were lower compared with the conventional methods. Finally, the efficiency for each method was investigated according to load variation and duty ratio D.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2005년도 전력전자학술대회 논문집
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• pp.549-551
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• 2005

Bidirectional DC/DC converters allows transfer of power between two dc sources, in either direction. Due to their ability to reverse the direction of flow of power, they are being increasingly used in many applications such as battery charger/dischargers, dc uninterruptible power supplies, electrical vehicle motor drives, aerospace power systems, telecom power supplies, etc. This paper proposes a new bidirectional Sepic/zeta converter. It has low swicthing loss and low conduction loss due to auxiliary communicated circuit and synchronous rectifier operation, respectively. Because of positive and buck/boost-like DC voltage transfer function(M=D/1-D), the proposed converter is very desirable for use in distributed power system . The proposed converter also has both transformerless version and transformer one.

• 공학기술논문지
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• 제5권4호
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• pp.349-353
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• 2012

Recently, Mobile multimedia equipments as smart phone and tablet pc requirement is increasing and this market is also being expanded. These mobile equipments require large multi-media function, so more power consumption is required. For these reasons, the needs of power management IC as switching type dc-dc converter and linear regulator have increased. DC-DC buck converter become more important in power management IC because the operating voltage of VLSI system is very low comparing to lithium-ion battery voltage. There are many people to be concerned about digital DC-DC converter without using external passive device recently. Digital controlled DC-DC converter is essential in mobile application to various external circumstance. This paper proposes the DC-DC Buck Converter using the AVR RISC 8-bit micro-processor control. The designed converter receives the input DC 18-30 [V] and the output voltage of DC-DC Converter changes by the feedback circuit using the A/D conversion function. Duty ratio is adjusted to maintain a constant output voltage 12 [V]. Proposed converter using the micro-processor control was compared to a typical boost converter. As a result, the current loss in the proposed converter was reduced about 10.7%. Input voltage and output voltage can be displayed on the LCD display to see the status of the operation.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2002년도 합동 추계학술대회 논문집 정보 및 제어부문
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• pp.609-612
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• 2002

In this paper, a 12-bit 100-MHz CMOS current steering digital-to-analog converter is designed. In the D/A converter, a driver circuit using a dynamic latch is implemented to obtain low glitch and thermometer decoder is used for low DNL errors, guaranteed monotonicity, reduced stitching noise. And a threshold voltage-compensated current source. The D/A converter is designed with 0.35-$\mu m$ CMOS technology at 3.3 V power supply and simulated with HSPICE. The maximum power dissipation of the designed DAC is 143 mW.

• Journal of electromagnetic engineering and science
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• 제9권2호
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• pp.98-104
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• 2009

An InGaP/GaAs MMIC LC VCO designed with Harmonic Noise Frequency Filtering(HNFF) technique is presented. In this VCO, internal inductance is found to lower the phase noise, based on an analytic understanding of phase noise. This VCO directly drives the on-chip double balanced mixer to convert RF carrier to IF frequency through local oscillator. Furthermore, final power performance is improved by output amplifier. This paper presents the design for a 1.721 GHz enhanced LC VCO, high power double balance mixer, and output amplifier that have been designed to optimize low phase noise and high output power. The presented asymmetric inductance tank(AIT) VCO exhibited a phase noise of -133.96 dBc/Hz at 1 MHz offset and a tuning range from 1.46 GHz to 1.721 GHz. In measurement, on-chip down-converter shows a third-order input intercept point(IIP3) of 12.55 dBm, a third-order output intercept point(OIP3) of 21.45 dBm, an RF return loss of -31 dB, and an IF return loss of -26 dB. The RF-IF isolation is -57 dB. Also, a conversion gain is 8.9 dB through output amplifier. The total on-chip down-converter is implanted in 2.56${\times}$1.07 mm$^2$ of chip area.