• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.12 s.354
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• pp.15-22
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• 2006

In this paper, 1.8V 8-bit 500MSPS Low-power CMOS Digital-to-Analog Converter(DAC) for UWB(Ultra Wide Band) Communication Systeme is proposed. The architecture of the DAC is based on a current steering 6+2 full matrix type which has low glitch and high linearity. In order to achieve a high speed and good performance, a current cell with a high output impedance and wide swing output range is designed. Further a thermometer decoder with same delay time and low-power switching decoder for high efficiency performance are proposed. The proposed DAC was implemented with TSMC 0.18um 1-poly 6-metal N-well CMOS technology. The measured SFDR was 49dB when the output frequency was 50MHz at 500MS/s sampling frequency. The measured INL and DNL were 0.9LSB and 0.3LSB respectively. The DAC power dissipation was 20mW and the effective chip area was $0.63mm^2$.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.13 no.2
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• pp.801-807
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• 2012

In this paper, design and implementation of frequency down converter based on LC filter technic. Single frequency down converter, designed a low-noise amplifier, mixer, IF amplifier, LC filter was configured. And it is composed of DC block capacitors and RF bypass capacitor. LC filter, replace it with the IC reduced the power and realized low cost. The gain of single down converter is about 10dBm and realized by 18MHz bandwidth at 70MHz band.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.23 no.1
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• pp.76-84
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• 2012

In this paper, two kinds of E-plane microstrip-to-waveguide transitions are optimally designed and fabricated for combining output power from multiple small-power amplifiers in a WR-28 waveguide because conventional K connectors cause unnecessary insertion loss and adaptor loss. The transition design is based on target specifications such as a center frequency of 35 GHz, bandwidth of ${\pm}500MHz$, 0.1 dB insertion loss and 20 dB return loss. Performance variation caused by mechanical tolerance and assembly deviation is fully evaluated by three dimensional electromagnetic simulation. The fabricated back-to-back transitions with 16 mm and 26.57 mm interstage microstrip lines show insertion loss per transition of ~0.1 dB at 35 GHz and average 0.2 dB over full Ka band. Also the back-to-back transition shows return loss greater than 15 dB, which implies that the transition itself has return loss better than 20 dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.24 no.3
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• pp.259-269
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• 2013

In this paper, we propose an SIW(Substrate Integrated Waveguide) multi-section E-plane transformer using air-holes for an SIW system with variable thicknesses. Air-holes are inserted into a SIW E-plane quarter wavelength transformer for matching an E-plane impedance discontinuity. A PSIW(Punched Substrate Integrated Waveguide) consisted of air-holes has an SIW characteristic impedance tunability because of reducing a equivalent shunt capacitance of the SIW. And, a PSIW multi-section E-plane transformer is implemented for improving a matching bandwidth by using the Chebyshev polynomial. The measurement results of PSIW double-section E-plane transformer show that the insertion loss($S_{21}$) is $1.57{\pm}0.11$ dB and input return loss($S_{11}$) is more than 15 dB from 11.45 GHz to 13.6 GHz.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.6
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• pp.271-275
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• 2014

A New Single Phase Active Power Filter Controller is proposed using Rotating Synchronous Frame d-q transformation. Instantaneous Active Power is calculated using d-q transformation. Average Value of Instantaneous Active Power is obtained using Low Pass Filter. Because power factor is corrected, source current is in phase with source voltage. Amplitude of source current is calculated using single phase power formula. Reference signal of compensated current of Active power filter is obtained from source current reference signal minus load current. Simulation is performed using hysteresis current controller in proposed new controller. Simulation result shows that because active power filter compensates load current, source current is in phase with source voltage and source current is sinusoidal. And Hilbert transformer is builded using all pass filter.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.1C
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• pp.14-23
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• 2003

This thesis proposes a sigma-delta modulator architecture with 2 Ms/s data rate and 12 bit resolution. A sigma-delta modulate has the features of oversampling and noise shaping. With these features, it can be connected with low resolution A/D converter to achieve higher resolution A/D converter. Most previous researches have been concentrated on high resolution but low data rate applications, e.g. audio applications. But, in order to be applied to various applications such as wireless data communication, researches on sigma-delta modulator architecture for higher data rate are required. The proposed sigma-delta modulator architecture has the sampling rate of 16 times Nyquist rate to achieve high data rate, and consists of a cascade of two 2nd order sigma-delta modulator to get relatively high resolution. The experimental result shows that the proposed architecture achieves 12-bit resolution at 2 Ms/s data rate.

• Journal of the Korean Society of Fisheries and Ocean Technology
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• v.34 no.1
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• pp.85-95
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• 1998

The broadband ultrasonic transducers have been designed to use in obtaining the broadband echo signals from fish schools in relation to the identification of fish species. The broadening of bandwidth was achieved by attaching double acoustic matching layers on the front face of a Tonpilz transducer consisted of an aluminum head, a piezoelectric ring, a brass tail and to evaluate the performance characteristics, such as the transmitting voltage response(TVR) of transducers. The constructed transducers were tested experimentally and numerically by changing the parameters such as impedances and thicknesses of the head, tail and matching layers, in the water tank. Also, the developed transducer was excited by a chirp signal and the received chirp waveforms were analyzed. According to the measured TVR results, the available 3 dB bandwidth of the transducer with double matching layers of an $Al_O_3/epoxy$ composite of 7 mm thick and a polyurethane window of 18 mm thick was 7.3 kHz with a center frequency of 38.8 kHz, and the maximum and the minimum values of the TVR in this frequency region were 135.7 dB and 132.7 dB re $1\;{\mu}Pa/V$ at 1 m, respectively. Also, the available 3 dB bandwidth of the transducer with double matching layers of an $Al_O_3/epoxy$ composite of 11 mm thick and a polyurethane window of 15 mm thick was 6.2 kHz with a center frequency of 38.6 kHz, and the maximum TVR value in the frequency region was 136.3 dB re $1\;{\mu}Pa/V$ at 1 m. Reasonable agreement between the experimental results and the numerical results for the TVR of the developed transducers was achieved. The frequency dependant characteristics of experimentally observed chirp signals closely matched to the measured TVR results. These results suggest that there is potential for increasing the bandwidth by varying other parameters in the transducer design and the material of the acoustic matching layers.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.843-852
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• 2009

In this paper, we present design, fabrication, and measured results for a frequency upconverter for a wireless communication system of UAV(Unmanned Aerial Vehicle). The specifications of such wireless communication system requires the special features of maximum range of communication as well as deployment in UAV and repairing. The frequency upconverter operating at $5.25{\sim}5.45\;GHz$ in C-band was designed and fabricated considering such special features. The AGC function was included because the required output power should be constant for optimal system operation. The fabricated upconverter showed a constant output power of $+2{\pm}0.5\;dBm$ for the $-15{\sim}-10\;dBm$ input. Spuriouses were below -60 dBc and the adjacent leakage power was below -40 dBc. In addition, LO sources in the upconverter was implemented using the frequency synthesizer with step 1 MHz. This is for the application to the situation where multiple UAVs employed and the possible change of the permitted frequency band. The synthesizer showed a phase noise of -100 dBc/Hz at the 100 kHz frequency offset.

• The Journal of the Korea institute of electronic communication sciences
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• v.11 no.1
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• pp.23-28
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• 2016

In this paper, a Multi-Band Ku-band down converter was designed for reception of multi-band digital satellite broadcasting. The Multi-band low-nose down converter was designed to form four local oscillator frequencies (9.75, 10, 10.75 and 11.3GHz) representing a low phase noise due to VCO-PLL with respect to input signals of 10.7 to 12.75GHz and 3-stage low noise amplifier circuit by broadband noise matching, and to select an one band of intermediate frequency (IF) channels by digital control. The developed low-noise downconverter exhibited the full conversion gain of 64dB, and the noise figure of low-noise amplifier was 0.7dB, the P1dB of output signal 15dBm, and the phase noise -73dBc@100Hz at the band 1 carrier frequency of 9.75GHz. The low noise block downconverter (LNB) for receiving four-band digital satellite broadcasting designed in this paper can be used for satellite broadcasting of vessels navigating international waters.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.2
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• pp.47-52
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• 2017

In this paper, CMOS SAR A/D converter 1.8V supply for the design of an A/D converter having an middle speed for the biological signal processing was designed. This paper proposes design of a 10-bit SAR Analog to Digital Converter improving linearity driven by MSB node of C-DAC array divided into 4 equal parts. It enhances linearity property, by retaining the analog input signal charging time at MSB node. Because MSB node samples analog input, it enhances resolution through getting initial input signal precisely. By using split capacitor on C-DAC array, it reduced chip size and power dissipation. The Proposed SAR A/D Converter is fabricated in 0.18um CMOS and measured 7.5 bits of ENOB at sampling frequency 4MS/s and power supply of 1.8V. It occupies a core area of $850{\times}650um^2$ and consumes 123.105uW. Therefore it results in 170.016fJ/step of FOM(Figure of Merit).