• 제어로봇시스템학회:학술대회논문집
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• 1996.10b
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• pp.1024-1027
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• 1996

The cyclic production lines have the first machines starved and the last machine blocked due to the lack or the excess of empty pallets in the feedback buffer. A workpiece in the cyclic production lines is transported on a pallet, and the total sum of pallets in the system does not changed during the system operation time. Therefore, the production rate of the cyclic production lines are dependent on the total number of pallets in the system. In this paper, we suggest the performance analysis method for the cyclic production lines with inspection machines and the optimal total number of pallets in the system that maximizes the production rate of the system. Finally, we validate the suggested methods by simulations.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.60 no.2
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• pp.315-319
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• 2011

A switched-capacitor cyclic DAC scheme with mismatch compensation of capacitors is designed. In cyclic DAC, a little error between two capacitors is accumulated every cycle. As a result, the accumulated error influences the final analog output which is wrong data. Therefore, a mismatch compensation technique was proposed and the error can be effectively reduced, which alleviates the matching requirement. In order to verify the operation of the proposed DAC, an 8-bit switched-capacitor cyclic DAC is designed through HSPICE simulation and implemented through magna 0.18um standard CMOS process.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.10 no.9
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• pp.1538-1544
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• 2006

This paper proposes a non-systolic parallel $AB^2+C$ Computing unit based on irreducible AOP order m of $GF(2^m)$. Proposed circuit have only AND gates and EX-OR gates, composes of cyclic shift operation, multiplication operation power operation power-sum operation and addition operation using a merry irreducible AOP. Suggested operating a method have an advantage high speed data processing, low power and integration because of only needs AND gates and EX-OR gates. $AB^2+C$ computing unit has delay-time of $T_A+(1+[log^m_2])T_X$.

• Progress in Superconductivity and Cryogenics
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• v.18 no.3
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• pp.30-34
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• 2016

An integral crank driven Stirling cryocooler is solidly based on concepts of direct IR detector mounting on the cryocooler's cold finger, and the integral construction of the cryocooler and Dewar envelope. Performance factors of the cryocooler depend on operating conditions of the cryocooler such as a cyclic mean pressure of the working fluid, a rotational speed of driving mechanism, a thermal environment, a targeted operation temperature and etc.. At given charging condition of helium gas, the cyclic mean pressure of helium gas in the cryocooler changes with temperatures of the cold end and the environment. In this study, effects of the cyclic mean pressure of helium gas on performances of the Stirling cryocooler were investigated by numerical analyses using the Sage software. The simulation model takes into account thermodynamic losses due to an inefficiency of regenerator, a pressure drop, a shuttle heat transfer and solid conductions. Simulations are performed for the performance variation according to the cyclic mean pressure induced by the temperature of the cold end and the environment. This paper presents P-V works in the compression and expansion space, cooling capacity, contribution of losses in the expansion space.

• Journal of the Semiconductor & Display Technology
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• v.17 no.1
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• pp.50-53
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• 2018

Cyclic measurement system using relay circuit for organic light emitting diode (OLED) was demonstrated. The OLED characterization such as current-voltage, impedance, and capacitance-voltage is performed in sequence, repetitively and automatically under full control of the personnel computer (PC) without changing the connection of cables. Owing to in situ degradation by cyclic measurement, the time dependence of the data can give good information on the reliability factor of the OLED devices. Therefore, both performance and reliability of the OLEDs can be evaluated, with no manual operation during the entire process.

• Journal of Ocean Engineering and Technology
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• v.9 no.1
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• pp.101-110
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• 1995

In SMA(Shape Memory Alloy), the degradation by fatigue is one of the most important problems to be overcome, when SMA is used for robot-actuator materials. The actuator is operated repetitively for long time and its repeating operation develops the fatigue degradation of SMA. The fatigue degradation changes the transformation temperature and deformation behavior and results in inaccurate operation and deformation which results form repeating operation is to be investigated in advance and the scheme to resolve those problems have to be made for the design of actuator. In this paper, for the improvement of the fatigue degradation by repetive movement and better control of the correct movement by the stability of martensite transformation in the development of Robots actuator, Pre-strain(0, 1.5, 5, 8%) are loaded in the specimens and fatigue testing were carried out by the method of heating and cooling in direct condition. From the results of these experiments, the effect on pre-strain which affect the transformation characteristic and fatigue degradation phenomena were correctly investigated.

• Nuclear Engineering and Technology
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• v.54 no.1
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• pp.177-185
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• 2022

Hydrogen risk in the containment filtered venting system (CFVS) vessel was analyzed, considering operation pressure and modes with the effect of PAR and accident scenarios. The CFVS is to depressurize the containment by venting the containment atmosphere through the filtering system. The CFVS could be subject to hydrogen risk due to the change of atmospheric conditions while the containment atmosphere passes through the CFVS. It was found that hydrogen risk increased as the CFVS opening pressure was set higher because more combustible gases generated by Molten Core Concrete Interaction flowed into the CFVS. Hydrogen risk was independent of operation modes and found only at the early phase of venting both for continuous and cyclic operation modes. With PAR, hydrogen risk appeared only at the 0.9 MPa opening pressure for Station Black-Out accidents. Without PAR, however, hydrogen risk appeared even with the CFVS opening set-point of 0.5 MPa. In a slow accident like SBO, hydrogen risk was more threatening than a fast accident like Large Break Loss-of-Coolant Accident. Through this study, it is recommended to set the CFVS opening pressure lower than 0.9 MPa and to operate it in the cyclic mode to keep the CFVS available as long as possible.

• Journal of the Institute of Electronics and Information Engineers
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• v.54 no.6
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• pp.30-39
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• 2017

A digital calibration technique based on digital-domain averaging for cyclic ADC is proposed. The proposed calibration compensates for nonlinearity of ADC due to capacitance mismatch of capacitors in 1.5-bit/stage MDAC. A 1.5-bit/stage MDAC with non-matched capacitors has symmetric residue plots with respect to the ideal residue plot. This intrinsic characteristic of residue plot of MDAC is reflected as symmetric A/D transfer functions. A corrected A/D transfer function can be acquired by averaging two transfer functions with non-linearity, which are symmetric with respect to the ideal analog-digital transfer function. In order to implement the aforementioned averaging operation of analog-digital transfer functions, a 12-bit cyclic ADC of this work defines two operational modes of 1.5-bit/stage MDAC. By operating MDAC as the first operational mode, the cyclic ADC acquires 12.5-bits output code with nonlinearity. For the same sampled input analog voltage, the cyclic ADC acquires another 12.5-bits output code with nonlinearity by operating MDAC as the second operational mode. Since analog-digital transfer functions from each of operational mode of 1.5-bits/stage MDAC are symmetric with respect to the ideal analog-digital transfer function, a corrected 12-bits output code can be acquired by averaging two non-ideal 12.5-bits codes. The proposed digital calibration and 12-bit cyclic ADC are implemented by using a $0.18-{\mu}m$ CMOS process in the form of full custom. The measured SNDR(ENOB) and SFDR are 65.3dB (10.6bits) and 71.7dB, respectively. INL and DNL are measured to be -0.30/-0.33LSB and -0.63/+0.56LSB, respectively.

• Geomechanics and Engineering
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• v.37 no.4
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• pp.383-393
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• 2024

Monopile foundations of offshore wind turbines embedded in soft clay are subjected to the long-term cyclic lateral loads induced by winds, currents, and waves, the vibration of monopile leads to the accumulation of pore pressure and cyclic strains in the soil in its vicinity, which poses a threat to the safety operation of monopile. The researchers mainly focused on the hysteretic stress-strain relationship of soft clay and kinds of stiffness degradation models have been adopted, which may consume considerable computing resources and is not applicable for the long-term bearing performance analysis of monopile. In this study, a modified cyclic stiffness degradation model considering the effect of plastic strain and pore pressure change has been proposed and validated by comparing with the triaxial test results. Subsequently, the effects of cyclic load ratio, pile aspect ratio, number of load cycles, and length to embedded depth ratio on the accumulated rotation angle and pore pressure are presented. The results indicate the number of load cycles can significantly affect the accumulated rotation angle of monopile, whereas the accumulated pore pressure distribution along the pile merely changes with pile diameter, embedded length, and the number of load cycles, the stiffness of monopile can be significantly weakened by decreasing the embedded depth ratio L/H of monopile. The stiffness degradation of soil is more significant in the passive earth pressure zone, in which soil liquefaction is likely to occur. Furthermore, the suitability of the "accumulated rotation angle" and "accumulated pore pressure" design criteria for determining the required cyclic load ratio are discussed.

• Journal of information and communication convergence engineering
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• v.5 no.2
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• pp.112-115
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• 2007

A CMOS TDC(time-to-digital converter) is proposed which has a simple cyclic structure. The proposed TDC consists of pulse-shrinking elements, D latches and D flip-flops. The operation is based on pulse-shrinking of the input pulse. The resolution of digital output can be easily improved by increasing the number of the pulse-shrinking elements, D latches and D flip flops. The TDC performance is improved in viewpoints of power consumption and chip area. Simulation results are shown to illustrate the performance of the proposed TDC circuit.