• Proceedings of the KIPE Conference
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• 2004.11a
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• pp.96-100
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• 2004

This paper deals with power quality disturbance generator with phase jump function. The proposed generator can be applied to the performance test of custom power devices. Voltage sag, swell, outage, unbalance and phase jump after outage are provided by the generator. The phase jump operating principle of the generator is described and analysed. The control scheme of the disturbance generator is simple and hardware setup is cost effective compared with the conventional scheme. The usefulness of the generator is verified through simulation and experimental results.

• Proceedings of the KIPE Conference
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• 2005.07a
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• pp.552-554
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• 2005

This paper deals with a simple structured voltage disturbance generator for power quality improving devices. The proposed generator can be applied to the performance test of custom power devices. Voltage sag, swell, outage, unbalance and phase jump after outage are provided by the generator. The improving phase jump operating principle of the generator is described and analysed. The usefulness of the generator is verified through simulation.

• The Transactions of the Korean Institute of Power Electronics
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• v.4 no.6
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• pp.601-607
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• 1999

본 논문에서는 순간전압조정, 역률 보상, 고조파 저감에 대한 배전용 정지형 동기조상기(STATCOM : STATic COMpensator)에 대한 다양한 제어 모드를 제안하고 있다. 이러한 제어 알고리즘의 성능을 검증하기 위해 각 제어 알고리즘을 20kVA의 축소형 STATCOM에 적용하고 간단한 배전계통을 꾸며 시험하였다. 실험결과로부터 제안한 제어알고리즘이 Custom Power 시스템으로 훌륭한 성능을 보임을 확인할 수 있었다. 실재 배전계통에 적용하여 현재 1MVA STATCOM이 성공적으로 운전되고 있다.

• Journal of rehabilitation welfare engineering & assistive technology
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• v.7 no.2
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• pp.13-18
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• 2013

In this paper design a 8 bit Current Steering D/A Converter for stimulating neuron signal. Proposed circuit in paper shows the conversion rate of 10KS/s and the power supply of 3.3V with 0.35um Magna chip CMOS process using full custom layout design. It employes segmented structure which consists of 3bit thermometer decoders and 5bit binary decoder for decreasing glitch noise and increasing resolution. So glitch energy is down by $10nV{\bullet}sec$ rather than binary weighted type DAC. And it makes use of low power current stimulator because of low LSB current. And it can make biphasic signal by connecting with Micro Controller Unit which controls period and amplitude of signal. As result of measurement INL is +0.56/-0.38 LSB and DNL is +0.3/-0.4 LSB. It shows great linearity. Power dissipation is 6mW.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.2
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• pp.323-329
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• 2002

This paper describes an efficient error-compensation technique for designing a low-error truncated Booth multiplier which produces an N-bit output from a two's complement multiplication of two N bit inputs by eliminating the N least-significant bits. Applying the proposed method, a truncated Booth multiplier for area-efficient and low-power applications has been designed, and its performance(truncation error, area) was analyzed. Since the truncated Booth multiplier does not have about half the partial product generators and adders, it results an area reduction of about 35％, compared with no-truncated parallel multipliers. Error analysis shows that the proposed approach reduces the average truncation error by approximately 60％, compared with conventional methods. A 16-b$\times$16-b truncated Booth multiplier core is designed on full-custom style using 0.35-${\mu}{\textrm}{m}$ CMOS technology. It has 3,000 transistors on an area of 330-${\mu}{\textrm}{m}$$\times$262-${\mu}{\textrm}{m}$ and 20-㎽ power dissipation at 3.3-V supply with 200-MHz operating frequency.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.2
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• pp.97-105
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• 2016

Microcontrollers (MCUs) for endpoint smart sensor devices of internet-of-thing (IoT) are being implemented as system-on-chip (SoC) with on-chip instruction flash memory, in which user firmware is embedded. MCUs directly fetch binary code-based instructions through bit-line sense amplifier (S/A) integrated with on-chip flash memory. The S/A compares bit cell current with reference current to identify which data are programmed. The S/A in reading '0' (erased) cell data consumes a large sink current, which is greater than off-current for '1' (programmed) cell data. The main motivation of our approach is to reduce the number of accesses of erased cells by binary code level transformation. This paper proposes a built-in write/read path architecture using binary code inversion method based on hot-spot region detection of instruction code access to reduce sensing current in S/A. From the profiling result of instruction access patterns, hot-spot region of an original compiled binary code is conditionally inverted with the proposed bit-inversion techniques. The de-inversion hardware only consumes small logic current instead of analog sink current in S/A and it is integrated with the conventional S/A to restore original binary instructions. The proposed techniques are applied to the fully-custom designed MCU with ARM Cortex-M0$^{TM}$ using 0.18um Magnachip Flash-embedded CMOS process and the benefits in terms of power consumption reduction are evaluated for Dhrystone$^{TM}$ benchmark. The profiling environment of instruction code executions is implemented by extending commercial ARM KEIL$^{TM}$ MDK (MCU Development Kit) with our custom-designed access analyzer.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.3A
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• pp.360-367
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• 2006

In this paper, we designed a digital codec of an RFID tag for EPC global generation 2 class 1. There are a large number of studies on RRD standard and anti-collision algorithm but few studies on the design of digital parts of the RFID tag itself. For this reason, we studied and designed the digital codec hardware for EPC global generation 2 class 1 tag. The purpose of this paper is not to improve former studies but to present the hardware architecture, an estimation of hardware size and power consumption of digital part of the RFID tag. Results are synthesized using Synopsys with a 0.35um standard cell library. The hardware size is estimated to be 111640 equivalent inverters and dynamic power is estimated to be 10.4uW. It can be improved through full-custom design, but we designed using a standard cell library because it is faster and more efficient in the verification and the estimation of the design.

• KIPS Transactions on Software and Data Engineering
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• v.6 no.8
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• pp.385-390
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• 2017

Because of the ever-increasing software complexity, model-based development techniques are becoming an essential technique in software development. However, even if model-based techniques are used, the test case generation for complex software is still a challenge to solve. In this paper, we propose a method to generate automatic test cases based on UML model using custom parser and SMT solver. By proposed technique, a test case can be generated even though the model is described in a platform independent language such as action language, or in a platform dependent language. In addition, a concolic execution technique is applied to efficiently generate test cases in the model. In this paper, we present a case study on the power window switch model of Hyundai Santa Fe through the proposed test case generation technique.

• Journal of Power Electronics
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• v.19 no.2
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• pp.519-528
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• 2019

The unified power quality conditioner (UPQC) is an effective custom power device that is used at the point of common coupling to protect loads from voltage and current-related PQ issues. Currently, most researchers have studied series unit and parallel unit models and an idealized transformer model. However, the interactions of the series and parallel converters in AC-link are difficult to analyze. This study utilizes an equivalent transformer model to accomplish an electric connection of series and parallel converters in the AC-link and to establishes a precise unified mathematical model of the UPQC. The strong coupling interactions of series and parallel units are analyzed, and they show a remarkable dependence on the excitation impedance of transformers. Afterward, a feed-forward decoupling method based on a unified model that contains the uncertainty components of the load impedance is applied. Thus, this study presents an adaptive method to estimate load impedance. Furthermore, simulation and experimental results verify the accuracy of the proposed modeling and decoupling algorithm.

• Proceedings of the KIEE Conference
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• 2003.11a
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• pp.457-459
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• 2003

As a competitive power market has introduced, many energy management systems have been developed. This paper presents the web-based energy management system which is developed by our company. The users tan monitor and analysis their load information using our energy management system.