• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 2001.07a
• /
• pp.267-270
• /
• 2001

A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10$\mu\textrm{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sifted conventional LTIGBT and the conventional LTIGBT which has the width of 17$\mu\textrm{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17$\mu\textrm{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field in the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
• /
• 1998.11a
• /
• pp.145-150
• /
• 1998

8$\times$8 bit scaled SONOSFET NAND type flash EEPROM that shows better characteristics on cell density and endurance than NOR type have been designed and its electrical characteristics are verified with computer aided simulation. For the simulation, the spice model parameter was extracted from the sealed down SONOSFET that was fabricated by $1.5mutextrm{m}$ topological design rule. To improve the endurance of the device, the EEPROM design to have modified Fowler-Nordheim tunneling through the whole channel area in Write/Erase operation. As a result, it operates Write/Erase operation at low current, and has been proven Its good endurance. The NAND type flash EEPROM, which has upper limit of V$_{th}$, has the upper limit of V$_{th}$ as 4.5V. It is better than that of floating gate as 4V. And a EEPROM using the SONOSFET without scaling (65$\AA$-l65$\AA$-35$\AA$), was also designed and its characteristics have been compared. It has more possibliity of error from the V$_{th}$ upper limit as 4V, and takes more time for Read operation due to low current. As a consequence, it is proven that scaled down SONOSFET is more pertinent than existing floating gate or SONOSFET without scaling for the NAND type flash EEPROM.EPROM.

• Current Industrial and Technological Trends in Aerospace
• /
• v.6 no.2
• /
• pp.80-89
• /
• 2008

Photogrammetry is a non-direct 3-dimensional coordinate measurement technique using 2-dimensional photographic images. For reconstruction 3-dimensional data from the 2-dimensional photos, photogrammetry uses the fundamental principle of triangulation. Digital photogrammetry solve for the camera location and coordinates simultaneously through the mapping, scaling and bundle processing in software processing. In this paper, several applications for photogrammetry measurement are introduced, such as 'photogrammetric measurement of the gravity deformation of a cassegrain type antenna', 'analysis of photogrammetry data from ISIM mockup', 'underwater photogrammetric verification of nuclear fuel assemblies', 'spacecraft optical bench measurement' and 'spacecraft ground support equipment measurement'.

• Progress in Superconductivity and Cryogenics
• /
• v.18 no.2
• /
• pp.8-13
• /
• 2016

Superconducting properties of thin film MgB2 superconductors irradiated with 45 MeV ${\alpha}$-particle beam were studied. After the irradiation, enhancement of the critical current density and pinning force was observed, scaling close to strong pinning formula. Double logarithmic plots of the maximum pinning force density with irreversible magnetic field show a power law behavior close to carbon-doped MgB2 film or polycrystals. Variation of normalized pinning force density in the reduced magnetic field suggests scaling formulas for strong pinning mechanism like planar defects. We also observed a rapid decay of critical current density as the vortex lattice constant decreases, due to the strong interaction between vortices and increasing magnetic field.

• The Bulletin of The Korean Astronomical Society
• /
• v.41 no.1
• /
• pp.81.2-81.2
• /
• 2016

Many signals in the nature have power-law behaviors, namely they are "scale-free". The method of detrended fluctuation analysis (DFA), as one of the popular methods (e.g., Rescaled range analysis and Spectral analysis) for determining scale-free nature of time series, has a very important advantage that the DFA can be applied to both stationary and non-stationary signals. The analysis of time series using the DFA has been broadly used in physiology, finance, hydrology, meteorology, geology, and so on. We performed the DFA of 16 Spaceweather HMI Active Region Patch (SHARP) parameters for 38 HMI Active Region Patches (HARPs) obtained by Solar Dynamics Observatory (SDO) from May 2010 to June 2014. The main results from this study are as follows. (1) The most of the time series data are non-stationary. (2) The DFA scaling exponents of "mean vertical current density" for 38 HARPs have a negative correlation coefficient (-0.41) with flare index. (3) The DFA scaling exponents of parameters such as "Sum of the absolute value of net currents per polarity", "Absolute value of the net current helicity", and "Mean photospheric excess magnetic energy density" for the most active HARPs having more than 10 major flares, have positive correlation coefficients (0.64, 0.59, and 0.53, respectively) with the ratio of "the number of CMEs associated with major flares" to "the number of major flares". Physical interpretations on our results will be discussed.

• Transactions on Electrical and Electronic Materials
• /
• v.2 no.4
• /
• pp.15-18
• /
• 2001

A new small scaling Lateral Trench Insulated Gate Bipolar Transistor (SSLTIGBT) was proposed to improve the characteristics of the device. The entire electrode of the LTIGBT was replaced with a trench-type electrode. The LTIGBT was designed so that the width of device was no more than 10 ${\mu}{\textrm}{m}$. The latch-up current densities were improved by 4.5 and 7.6 times, respectively, compared to those of the same sized conventional LTIGBT arid the conventional LTIGBT which has the width of 17 ${\mu}{\textrm}{m}$. The enhanced latch-up capability of the SSLTIGBT was obtained due to the fact that the hole current in the device reaches the cathode via the p+ cathode layer underneath the n+ cathode layer, directly. The forward blocking voltage of the SSLTIGBT was 125 V. At the same size, those of the conventional LTIGBT and the conventional LTIGBT with the width of 17 ${\mu}{\textrm}{m}$ were 65 V and 105 V, respectively. Because the proposed device was constructed of trench-type electrodes, the electric field In the device were crowded to trench oxide. Thus, the punch through breakdown of LTEIGBT occurred late.

• JSTS:Journal of Semiconductor Technology and Science
• /
• v.9 no.2
• /
• pp.110-116
• /
• 2009

The prominent advantages of Dual Material Surrounding Gate (DMSG) MOSFETs are higher speed, higher current drive, lower power consumption, enhanced short channel immunity and increased packing density, thus promising new opportunities for scaling and advanced design. In this Paper, we present Transconductance-to-drain current ratio and electric field distribution model for dual material surrounding gate (DMSGTs) MOSFETs. Transconductance-to-drain current ratio is a better criterion to access the performance of a device than the transconductance. This proposed model offers the basic designing guidance for dual material surrounding gate MOSFETs.

• Proceedings of the Earthquake Engineering Society of Korea Conference
• /
• 2002.03a
• /
• pp.75-82
• /
• 2002

Shaking table model tests are performed to reproduce the dynamic behavior of a gravity quay wall and a pile-supported wharf damaged by Kobe earthquake in 1995. Using the scaling relations suggested by Scott and Iai(1989), the results of the model tests are compared with field measurements as well as with those of the model tests previously executed. The displacements of the gravity quay wall predicted by the current model tests are, at most, one third of the measured displacements, while the displacements of the model pile-supported wharf are about two thirds of the measured values. One possibility for the discrepancy is speculated to be the use of too big scaling factor, i.e., too small size of model.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
• /
• 2000.10a
• /
• pp.480-484
• /
• 2000

The channel length influence of n-channel Si-based FETs is investigated by computer simulation. Using a two-dimensional hydrodynamic model, devices having various gate length are examined. We have observed the characteristics of LDD model of MOSFET by investigating of their current, voltage, electric field and impact ionization. These devices are scaled using various factors. We have analyzed I-V characteristics and the effect of impact ionization according to channel length.

• 한국정보디스플레이학회:학술대회논문집
• /
• 2006.08a
• /
• pp.399-402
• /
• 2006

A new voltage-scaled compensation pixel which employs 3 p-type poly-Si TFTs and 2 capacitors without additional control line has been proposed and verified. The proposed pixel does not employ the $V_{TH}$ memorizing and cancellation, but scales down the inevitable $V_{TH}$ variation of poly-Si TFT. Also the troublesome narrow input range of $V_{DATA}$ is increased and the $V_{DD}$ supply voltage drop is suppressed. In our experimental results, the OLED current error is successfully compensated by easily controlling the proposed voltage scaling effects.