• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.1876-1879
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• 2003

Due to the conventional half-bridge switch-mode converters for dc motor drive have been usually using unbalanced circuit topologies which generate common-mode currents through parasitic capacitors distributed between the ground and the dc motor frame such as the heat-sink of switching devices or the frame of the dc motor. This paper describes methods that cancel common-mode current generated in half-bridge switch-mode converters by using circuit balancing technique. The circuit balancing is to make the noise pickup or occurring in both conductor lines, signal and return pathes, is equal in amplitude and opposite in phase so that it will be canceled out in the ground plane. The common-mode current cancellation in the proposed converter is confirmed by experimental results.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2003년도 ICCAS
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• pp.960-964
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• 2003

In this paper, the CMOS integrated circuit technique for implementing current-mode maximum and minimum operations scheme is described. The maximum and minimum operations are incorporated into the same scheme with parallel processing. Using this scheme as the basic unit, an analog three-input maximum, median, and minimum circuit is designed. The performance of the proposed circuit shows a very sharp transfer characteristic and high accuracy. The proposed circuit achieves a high-speed operation, which is suitable for real-time systems. The PSPICE simulation results demonstrating the characteristic of the proposed circuit are included.

• 전기학회논문지
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• 제57권7호
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• pp.1254-1259
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• 2008

A new CMOS current-mode integrator for low-voltage analog integrated circuit design is presented. The proposed current-mode integrator is based on cross-coupled gain-boosting topology. When it is compared with that of the typical current-mirror type current-mode integrator, the proposed current-mode integrator achieves high current gain and unity gain frequency with the same transistor size. As a application circuit of the proposed integrator, we designed the 1.8V 200MHz band current-mode lowpass filter. These are verified by Hspice simulation using $0.18{\mu}m$ CMOS technology.

• ETRI Journal
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• 제26권4호
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• pp.292-296
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• 2004

In this paper we present a new current-mode electronically tunable universal filter using only plus-type current controlled conveyors (CCCII+s) and grounded capacitors. The proposed circuit can simultaneously realize lowpass, bandpass, and highpass filter functions - all at high impedance outputs. The realization of a notch response does not require additional active elements. The circuit enjoys an independent current control of parameters $\omega_0$ and $\omega_0/Q$. No element matching conditions are imposed. Both its active and passive sensitivities are low.

• 전자공학회논문지C
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• 제34C권8호
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• pp.49-63
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• 1997

This paper presents a current sensor that detects defects in CMOS integrated circuits using the current testing technique. The current sensor is built in a CMOS integrated circuit to test an abnormal current. The proposed circuit has a very small impact on the performance of the circuit under test during the normal mode. In the testing mode, the proposed circuit detects the abnormal current caused by permanent manufacturing defects and determines whether the circuit under test is defect-free or not. The proposed current sensor is simple and requires no external voltage and current sources. Hence, the circuit has less area and performance degradation, and is more efficient than any previous works. The validity and effectiveness are verified through the HSPICE simulation on circuits with defects.

• 한국정보통신학회논문지
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• 제13권9호
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• pp.1837-1844
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• 2009

본 논문에서는 전류모드 CMOS에 의한 2변수 3치 가산기 회로와 승산기 회로를 구현하였다. 제시된 전류모드 CMOS에 의한 3치 가산기 회로와 승산기 회로는 전압 레벨로 동작하며, HSpice 시뮬레이션을 통하여 이 회로들에 대하여 동작 특성을 보였다. 제시 된 회로들은 $0.180{\mu}m$ CMOS 표준 기술을 사용하여 HSpice로 시뮬레이션 하였다. 2 변수 3치 가산기 및 승산기 회로의 단위 전류 $I_u$는 $5{\mu}A$로 하였으며, NMOS의 길이와 폭 W/L는 $0.54{\mu}m/0.18{\mu}m$이고, PMOS의 길이와 폭 W/L는 $1.08{\mu}m/0.18{\mu}m$이다. VDD 전압은 2.5V를 사용하였으며 MOS 모델은 LEVEL 47으로 시뮬레이션 하였다. 전류모드 CMOS 3치 가산기 및 승산기 회로의 시뮬레이션 결과에서 전달 지연 시간이 $1.2{\mu}s$이며, 3치 가산기 및 승산기 회로가 안정하게 동작하여 출력 신호를 얻는 동작 속도가 300MHz, 소비 전력이 1.08mW임을 보였다.

• Journal of Information Display
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• 제6권4호
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• pp.11-15
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• 2005

We propose a current mode logic circuit design method for LTPS TFT for enhancing circuit operating speed. Current mode inverter/buffers with passive resistive load had been designed and fabricated. Measurement results indicated that the smaller logic swing of the current mode allowed significantly faster operation than the static CMOS. In order to reduce the chip size, both all pTFT and all nTFT active load current mode inverter/buffer had been designed and analyzed by HSPICE simulation. Even though the active load current mode circuits were inferior to the passive load circuits, it was superior to static CMOS gates.

• 한국전자통신학회논문지
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• 제15권3호
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• pp.479-486
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• 2020

이 논문에서는 아날로그 전류모드 인공지능 프로세서에서 핵심 디바이스 중에 하나인 아날로그 전류 모드 곱셈기 회로의 선형성과 동적범위 향상을 위한 설계 기법을 소개한다. 제안하는 회로는 4 quadrant Translinear loop를 NMOS 트랜지스터만으로 구성하여, 트랜지스터의 물리적 Mismatch를 최소화하는 설계로 0.35㎛ CMOS 공정에서 117㎛ × 109㎛로 구현가능하였으며, 최대 전고조파왜율 0.3% 의 선형성을 확보할 수 있었다. 제안한 아날로그 전류모드 곱셈기는 전류모드 인공지능 프로세서의 핵심 회로로 유용할 것으로 기대된다.

• 한국전자통신학회논문지
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• 제3권2호
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• pp.79-85
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• 2008

다양한 무선통신 방식이 출현함에 따라 배터리 수명과, 저전력 동작이 중요시되면서 무선 통신용 LSI는 SI circuit을 이용하는 analog current-mode signal processing을 주목하고 있다. 그러나 SI (Switched-Current) circuit을 구성하는 current memory는 clock-feedthrough의 문제점을 갖는다. 본 논문에서는 current memory의 문제점인 clock-feedthrough의 일반적인 해결방안으로 CMOS switch의 연결을 검토하고, current memory 성능 개선의 설계방안을 제안하기 위하여 CMOS switch 간의 width의 관계를 도출하고자 한다. Simulation 결과, memory MOS의 width가 20um, input current와 bias current의 ratio가 0.3, CMOS switch nMOS의 width가 2~6um일 경우에 CMOS switch 간의 width는 $W_{Mp}=5.62W_{Mn}+1.6$의 관계로 정의되고, CMOS switch nMOS의 width가 6~10um일 경우에 CMOS switch 간의 width는 $W_{Mp}=2.05W_{Mn}+23$의 관계로 정의되는 것을 확인하였다. 이 때 정의된 MOS transistor의 관계는 memory MOS의 성능향상을 위한 설계에 유용한 지침이 될 것으로 기대된다.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2001년도 ICCAS
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• pp.108.6-108
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• 2001

The basic circuit block diagram of CMOS current mode sum and subtract circuit is present in this paper. The purpose circuit consists of the invert current circuit and the basic current mirror. The outputs of the circuit are the summing of the both input current [lx+ly] and also the subtract of the both input current [lx+(-ly)]. The SPICE simulation results of the electrical characteristics with level 7 (BSIM3 model version 3.1) MOSFET transistor model of the circuit such as the input dynamic range, the frequency response and some system application have been shown and analyzed.