• 대한전기학회:학술대회논문집
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• 대한전기학회 2006년 학술대회 논문집 정보 및 제어부문
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• pp.142-144
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• 2006

In this paper, the Ternary adder and multiplier are implemented by current-mode CMOS. First, we implement the ternary T-gate using current-mode CMOS which have an effective availability of integrated circuit design. Second, we implement the circuits to be realized 2-variable ternary addition table and multiplication table over finite fields GF(3) with the ternary T-gates. Finally, these operation circuits are simulated by Spice under $1.5{\mu}m$ CMOS standard technology, $1.5{\mu}m$ unit current, and 3.3V VDD voltage. The simulation results have shown the satisfying current characteristics. The ternary adder and multiplier implemented by current-mode CMOS are simple and regular for wire routing and possess the property of modularity with cell array.

• JSTS:Journal of Semiconductor Technology and Science
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• 제15권2호
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• pp.292-300
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• 2015

This paper proposes a high-efficiency, dual-mode PWM / linear buck converter with a wide-input range. The proposed converter was designed with a mode selector that can change the operation between PWM / linear mode by sensing a load current. The proposed converter operates in a linear mode during a light load and in PWM mode during a heavy load condition in order to ensure high efficiency. In addition, the mode selector uses a bit counter and a transmission gate designed to protect from a malfunction due to noise or a time-delay. Also, in conditions between $-40^{\circ}C$ and $140^{\circ}C$, the converter has variations in temperature of $0.5mV/^{\circ}C$ in the PWM mode and of $0.24mV/^{\circ}C$ in the linear mode. Also, to prevent malfunction and breakdown of the IC due to static electricity, the reliability of IC was improved by embedding a self-produced 8 kV-class(Chip level) ESD protection circuit of a P-substrate Triggered SCR type with high robustness characteristics.

• 전기학회논문지
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• 제58권7호
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• pp.1349-1355
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• 2009

This paper is studied on a novel power factor correction (PFC) AC-DC converter of high efficiency by soft switching technique. The input current waveform in the proposed converter is got to be a sinusoidal form composed of many a discontinuous pulse in proportion to the magnitude of a ac input voltage under the constant switching frequency. Therefore, the input power factor is nearly unity and the control method is simple. The proposed converter adding an electric isolation operates with a discontinuous current mode (DCM) of the reactor in order to obtain some merits of simpler control, such as fixed switching frequency, without synchronization control circuit used in continuous current mode (CCM). To achieve the soft switching (ZCS or ZVS) of control devices, the converter is constructed with a new loss-less snubber for a partial resonant circuit. It is that the switching losses are very low and the efficiency of the converter is high, Particularly, the stored energy in a loss-less snubber capacitor recovers into input side and increases input current from a resonant operation. The result is that the input power factor of the proposed converter is higher than that of a conventional PFC converter. This paper deals mainly with the circuit operations, theoretical, simulated and experimental results of the proposed PFC AC-DC converter in comparison with a conventional PFC AC-DC converter.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권4호
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• pp.528-533
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• 2016

A low voltage high PSRR CMOS Bandgap circuit capable of generating a stable voltage of less than 1 V (0.8 V and 0.5 V) robust to Process, Voltage and Temperature (PVT) variations is proposed. The high PSRR of the circuit is guaranteed by a low-voltage current mode regulator at the central aspect of the bandgap circuitry, which isolates the bandgap voltage from power supply variations and noise. The isolating current mirrors create an internal regulated voltage $V_{reg}$ for the BG core and Op-Amp rather than the VDD. These current mirrors reduce the impact of supply voltage variations. The proposed circuit is implemented in a $0.35{\mu}m$ CMOS technology. The BGR circuit occupies $0.024mm^2$ of the die area and consumes $200{\mu}W$ from a 5 V supply voltage at room temperature. Experimental results demonstrate that the PSRR of the voltage reference achieved -118 dB at frequencies up to 1 kHz and -55 dB at 1 MHz without additional circuits for the curvature compensation. A temperature coefficient of $60 ppm/^{\circ}C$ is obtained in the range of -40 to $120^{\circ}C$.

• Journal of Magnetics
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• 제16권3호
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• pp.246-252
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• 2011

A high-voltage power supply has been built for activation of the brain via stimulation using a Full Wave Cockroft-Walton Circuit (FWCW). A resonant half-bridge inverter was applied (with half plus/half minus DC voltage) through a bidirectional power transistor to a magnetic stimulation device with the capability of producing a variety of pulse forms. The energy obtained from the previous stage runs the transformer and FW-CW, and the current pulse coming from the pulse-forming circuit is transmitted to a stimulation coil device. In addition, the residual energy in each circuit will again generate stimulation pulses through the transformer. In particular, the bidirectional device modifies the control mode of the stimulation coil to which the current that exceeds the rated current is applied, consequently controlling the output voltage as a constant current mode. Since a serial resonant half-bridge has less switching loss and is able to reduce parasitic capacitance, a device, which can simultaneously change the charging voltage of the energy-storage condenser and the pulse repetition rate, could be implemented. Image processing of the brain activity was implemented using a graphical user interface (GUI) through a data mining technique (data mining) after measuring the vital signs separated from the frequencies of EEG and ECG spectra obtained from the pulse stimulation using a 90S8535 chip (AMTEL Corporation).

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2004년도 ICCAS
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• pp.504-508
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• 2004

An EMC analysis of a switched mode power supply (SMPS) have been usually using unbalance circuit topologies and the major factor of disturbance is parasitic capacitance. We have proposed a balanced switching converter circuit, which is an effective way to reduce the common mode conducted noise. In this paper presents the relationship between common mode current and radiated field.

• 전력전자학회논문지
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• 제5권5호
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• pp.443-450
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• 2000

PWM 인버터에 의하여 구동되는 유도전동기는 뛰어난 동작특성을 가지고 있지만, 커먼 모드 전압과 고주파 누설전류를 야기한다. 이 고주파 누설 전류는 여러가지 문제점을 일으킨다. 본 논문에서는 이러한 문제점을 일으키는 고주파 누설 전류와 커먼 모드 진압을 감쇄하기 위하여 커먼 모드 전압과 크기가 같고 반대극성을 가진 전압을 4 level half bridge 인버터를 이용하여 생성하고, 이것을 커먼 모드 transformer에 인가하여 고주파 누설 전류 역시 감쇄시킬 수 있는 새로운 형태의 능동형 커먼 모드 전압 감쇄기를 제안한다. 그리고 제안한 감쇄기의 동작 성능을 시뮬레이션과 실험을 통하여 검증하였다.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.89-92
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• 2001

In this paper, a simple low-power CMOS current reference circuit is proposed. The reference circuit includes parasitic pnp BJTs and resistors. Temperature compensation is made by adding a current component proportional to a thermal voltage to a current component proportional to a base-to-emitter voltage. The designed circuit has been simulated using a 0.25${\mu}{\textrm}{m}$ n-well CMOS process parameters. The simulation results show that the reference current is 34.96$mutextrm{A}$$\pm$0.04$mutextrm{A}$ in the temperature range of -2$0^{\circ}C$ to 12$0^{\circ}C$ The reference current varies less than 0.6% when the power supply voltage changes from 2.5V to 3.5V For $V_{DD=5V}$ and T=3$0^{\circ}C$ the power consumption is 520㎼ during normal operation but reduces to 0.l㎻ during power-down mode.

• JSTS:Journal of Semiconductor Technology and Science
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• 제3권3호
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• pp.139-144
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• 2003

We report the results of extensive mixed mode simulations and theoretical analysis to quantify the contribution of the edge direct tunneling (EDT) current on the total gate leakage current of 80nm NMOSFET with SiO2 gate dielectric. It is shown that EDT has a profound impact on basic analog circuit building blocks such as sample-hold (S/H) circuit and the current mirror circuit. A transistor design methodology with zero gate-source/drain overlap is proposed to mitigate the EDT effect. This results in lower voltage droop in S/H application and better current matching in current mirror application. It is demonstrated that decreasing the overlap length also improves the basic analog circuit performance metrics of the transistor. The transistor with zero gate-source/drain overlap, results in better transconductance, input resistance, output resistance, intrinsic gain and unity gain transition frequency.

• 전자공학회논문지S
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• 제34S권9호
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• pp.118-125
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• 1997

This paper proposed a new partial resonant 3.PHI. AC-DC boost converter of high efficiency using lossless snubber. The proposed converter, DCM (Discontinuous Current Mode) has a merit of simple controlled circuit because the input current control discontinuously. But turned off switching loss and stress of the switching device increase when the switch turned off at the peak of current. Therefore, the paper improves efficiency by adopting the PRS$^{2}$(Partial Resonant Soft Switching) in 3.PHI. AC-DC boost converter and makes the unity power factor. The PRS$^{2}$ is reduced a current/voltage stresses of switching devices. Also, a DCMPRS$^{2}$M(Discontinuous Conduction Mode Partial Resonant Soft Switching Method) appear the current and voltage equation of this circuit. The paepr examine in a 3.PHI. AC-DC boost converter and show the result of that.