• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.11
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• pp.2100-2106
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• 2007

Multi-stage folding A/D converter circuit with $0.25{\mu}m$ N-well CMOS technology is designed. This A/D converter consists of a transconductance circuit, linear folder circuit and 1bit A/D converter circuit. In H-spice simulation results, linear folder circuits having high linearity can be obtained when the current mode is used instead of voltage mode. And in case of 6bit, the delay time is limited about 40ns. From this results, 6bit 25MSPS A/D converter circuit can be realized.

• Journal of the Institute of Electronics and Information Engineers
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• v.52 no.11
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• pp.36-43
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• 2015

A pixel-level readout circuit is studied for 2-dimensional microbolometer focal plane arrays (FPAs). A current mirroring injection (CMI) input circuit with 2-step current-mode bias suppression is proposed for a pixel-level architecture with high responsivity and long integration time. The proposed circuit has been designed using a $0.35-{\mu}m$ 2-poly 4-metal CMOS process for a $320{\times}240$ microbolometer array with a pixel size of $50{\mu}m{\times}50{\mu}m$. The proposed 2-step bias-current suppression has sufficiently low calibration error with wide calibration range, and the calibration range and error can be easily optimized by controlling some design parameters. Due to high responsivity and a long integration time of more than 1 ms, the noise equivalent temperature difference (NETD) of the proposed circuit can be improved to 26 mK, which is much better than that of the conventional circuits, 67 mK.

• Journal of Welding and Joining
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• v.15 no.6
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• pp.41-48
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• 1997

For analyzing the characteristics of arc welding processes, an algorithm is necessary to determine the metal transfer mode, arc stability and weld quality. In this study, the weight of spatter during welding was selected for determining the arc stability, which is very relevant to the occurrence of spatter. Weld spatter occurs mainly at the moment when the short circuit is formed and also when it is broken causing the arc to restrike. Based on this fact, the arc stability can be determined by finding the suitable parameters of welding current and arc voltage which influence the weight of spatter. Through various welding experiments, the peak current, the arcing time, the short circuit time, the current and its slope at the start of short circuit were found mainly to influence the weight of spatter. For the convenient usage, an index was proposed by combining all these parameters. It was found that the index is very effective for determining the arc stability.

• Journal of Electrical Engineering and Technology
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• v.10 no.5
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• pp.1989-2000
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• 2015

In this paper, digital peak current mode control for single phase H-bridge inverters is developed and implemented. The digital peak current mode control is achieved by directly controlling the PWM signals by cycle-by-cycle current limitation. Unlike the DC-DC converter where the output voltage always remains in the positive region, the output of DC-AC inverter flips from positive to negative region continuously. Therefore, when the inverter operates in negative region, the control should be changed to valley current mode control. Thus, a novel control logic circuit is required for the function and need to be analyzed for the hardware to track the sinusoidal reference in both regions. The problem of sub-harmonic instability which is inherent with peak current mode control is also addressed, and then proposes the digital slope compensation in constant-sloped external ramp to suppress the oscillation. For unipolar PWM switching method, an adaptive slope compensation in digital manner is also proposed. In this paper, the operating principles and design guidelines of the proposed scheme are presented, along with the performance analysis and numerical simulation. Also, a 200W inverter hardware prototype has been implemented for experimental verification of the proposed controller scheme.

• The Transactions of the Korean Institute of Power Electronics
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• v.10 no.3
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• pp.219-225
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• 2005

In this paper, a new discrete-time small signal model of an average current mode control is proposed to predict the inductor current responses. Compared to the peak current mode control, the analysis of the average current mode control is difficult because of its presence of an compensation network. By utilizing sampler model, a new discrete-time small signal model is derived and used to predict the behaviors of an inductor current of average current mode control employing generalized compensation networks. In order to show the usefulness of the proposed model, prediction results of the proposed model are compared to those of the circuit level simulator, PSIM and experiment.

• The Journal of the Korea institute of electronic communication sciences
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• v.8 no.10
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• pp.1477-1483
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• 2013

This paper proposes a low-voltage current-mode integrator for a continuous-time current-mode baseband channel selection filter. The low-voltage current-mode linear cascode integrator is introduced to offer advantages of high current gain and improved unity-gain frequency. The proposed current-mode integrator has fully differential input and output structure consisting of CMOS complementary circuit. Additional cascode transistors which are operated in linear region are inserted for bias to achieve the low-voltage feature. Frequency range is also controllable by selecting proper bias voltage. From simulation results, it can be noticed that the implemented integrator achieves design specification such as low-voltage operation, current gain, and unity gain frequency.

• Proceedings of the IEEK Conference
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• 2002.07a
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• pp.333-336
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• 2002

An alternative CMOS implementation of a multi-output four-terminal floating nullor (FTFN) with constant-g$_{m}$ rall-to-rail input stage is proposed. This presented circuit is based on the advantages of a complementary transconductance amplifier and class AB dual translinear cell circuit that comes up with wide bandwidth. The constant-g$_{m}$ characteristic is controlled by the maximum-current selection circuits, maintaining the smooth response over the change of input common mode voltage. The circuit performances are confirmed through HSPICE simulations. A current-mode multifunction filter is used to exhibit the potentiality of this proposed scheme.eme.

• Proceedings of the KIEE Conference
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• 2003.10b
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• pp.187-189
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• 2003

Conventional Switched Mode Power Supplies(SMPS) with diode-capacitor rectifier have distorted input current waveform with high harmonic content. Typically, these SMPS have a power factor lower than 0,65. To improve with this problem the power factor correction(PFC) circuit of power supplies has to be introduced. Specially. to the reduce size and manufacture cost of power conversion device, the single-stage PFC converter is increased to demand as necessary of study. in this paper, The comparative analysis of power factor correction circuit using Feedforward control with average current mode flyback converter(single-stage) and boost converter(two-stage). Also, the validity of designed and manufactured high power factor flyback converter and boost converter is confirmed by simulation and experimental results.

• Proceedings of the KIPE Conference
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• 1997.07a
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• pp.243-246
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• 1997

In this paper, soft switching high power factor buck converter is proposed. This converter is composed of diode rectifier, a input capacitor can be small enough to filter input capacitor can be small enough to filter input current, buck converter with loss less snubber circuit. Converter is operated in discontinous conduction mode, turn of of the switching device is a zero current switching(ZCS) and high power factor input is obtained. In addition, zero voltage switching(ZVS) at turn of is achieved and switching loss is reduced using loss less snubber circuit. The capacitor used in the snubber circuit raised output voltage. Therefore, proposed converter has higher output voltage and higher efficiency than conventional buck type converter at same duty factor in discontious conduction mode operation.

• Proceedings of the KIPE Conference
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• 2002.07a
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• pp.374-377
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• 2002

This paper presents dynamic analyses and control design of the current-mode controlled active-clamp forward-flyback converter. The circuit averaging technique is used to extract the small-signal circuit model for the power stage From the small-signal circuit model of the power stage, the open-loop transfer functions are derived and used for the compensation design. The analysis results are verified using an experimental converter that delivers a 3.3V/10A output from a $40\~60V$ input source.