• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.7
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• pp.115-121
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• 2013

We fabricated thin film transistors (TFTs) using TiInZnO(TiIZO) thin films as active channel layer. The thin films of TiIZO were deposited at room temperature by RF-magnetron co-sputtering system from InZnO(IZO) and Ti targets. We examined the effects of titanium addition by X-ray diffraction, X-ray photoelectron spectroscopy and the electrical characteristics of the TFTs. The TiIZO TFTs were investigated according to the radio-frequency power applied to the Ti target. We found that the transistor on-off currents were greatly influenced by the composition of titanium addition, which suppressed the formation of oxygen vacancies, because of the stronger oxidation tendency of Ti relative to that of Zn or In. A optimized TiIZO TFT with rf power 40W of Ti target showed good performance with an on/off current ratio greater than $10^5$, a field-effect mobility of 2.09 [$cm^2/V{\cdot}s$], a threshold voltage of 2.2 [V] and a subthreshold swing of 0.492 [V/dec.].

• The Journal of Korean Institute of Communications and Information Sciences
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• v.31 no.8A
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• pp.820-829
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• 2006

IP-based design methodology has been popularly employed for SoC design to reduce design complexity and to cope with time-to-market pressure. Due to the request for high performance of current mobile systems, embedded SoC design needs a multi-processor to manage problems of high complexity and the data processing such as multimedia, DMB and image processing in real time. Interface module for communication between system buses and processors are required, since many IPs employ different protocols. High performance processors require interface module to minimize the latency of data transmission during read-write operation and to enhance the performance of a top level system. This paper proposes an automatic interface generation system based on FSM generated from the common protocol description sequence of a bus and an IP. The proposed interface does not use a buffer which stores data temporally causing the data transmission latency. Experimental results show that the area of the interface circuits generated by the proposed system is reduced by 48.5% on the average, when comparing to buffer-based interface circuits. Data transmission latency is reduced by 59.1% for single data transfer and by 13.3% for burst mode data transfer. By using the proposed system, it becomes possible to generate a high performance interface circuit automatically.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 1993.05a
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• pp.79-84
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• 1993

This paper describes the development of lithium rechargeable cell. $LiCoO_2$ is recently recognized as a suitable cathode active material of a high voltage, high energy lithium rechargeable batteries because $Li^+$ ion can be electrochemically deintercalated/intercalated from/to $Li_xCoO_2$. The transition metal oxide of $LiCoO_2$ was investigated for using as a cathode active material of 4V class Li rechargeable cell. $LiCoO_2$ cathode was prepared by using a active material of 85 wt%, graphite powder of 12 wt% as a conductor and poly-vinylidene fluoride of 3 wt% as a binder. The electrochemical and charge/discharge properties of $LiCoO_2$ were investigated by cyclic voltammetry and galvanostatic charge/discharge. The open circuit voltage of prepared $LiCoO_2$ electrode exhibited approximately. potential range between 3.32V and 3.42V. During the galvanostatic charge/discharge, $LiCoO_2/Li$ cell showed stable cycling behavior at scan rate of 1mV/sec and potential range between 3.6V and 4.2V. Also its coulombic efficiency as function of cycling was 81%~102%. In this study the $LiCoO_2/Li$ cell showed the available discharge capacity of 90.1 mAh/g at current density of $1mA/cm^2$ and cell discharge voltage range between 3.6V~4.2V.

• Journal of the Korean Institute of Telematics and Electronics D
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• v.35D no.10
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• pp.39-50
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• 1998

Wide-band sharp-transition filters are widely used in applications such as wireless CODEC design or medical systems. Since these filters suffer from large sensitivity and roundoff noise, large word-length is required for the VLSI implementation, which increases the hardware size and the power consumption of the chip. In this paper, a low-power implementation technique for digital filters with wide-band sharp-transition characteristics is proposed using CPL (Complementary Pass-Transistor Logic), LWDF (Lattice Wave Digital Filter) and a modified DIFIR (Decomposed & Interpolated FIR) algorithm. To reduce the short-circuit current component in CPL circuits due to threshold voltage reduction through the pass transistor, three different approaches can be used: cross-coupled PMOS latch, PMOS body biasing and weak PMOS latch. Of the three, the cross-coupled PMOS latch approach is the most realistic solution when the noise margin as well as the energy-delay product is considered. To optimize CPL transistor size with insight, the empirical formulas for the delay and energy consumption in the basic structure of CPL circuits were derived from the simulation results. In addition, the filter coefficients are encoded using CSD (Canonic Signed Digit) format and optimized by a coefficient quantization program. The hardware cost is minimized further by a modified DIFIR algorithm. Simulation result shows that the proposed method can achieve about 38% reductions in power consumption compared with the conventional method.

• Journal of the Microelectronics and Packaging Society
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• v.17 no.3
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• pp.43-49
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• 2010

Direct printing technology is an attractive metallization method, which has become immerging as "Green technology" to the conventional photolithography, on account of low cost, simple process and environment-friendliness. In order to commercialize the printed electronics in industry, it is essential to evaluate the electrical properties of conductive circuits using direct printing technology. In this contribution, we focused on the electrical characteristics of inkjet-printed circuits. A Cu nanoink was inkjet-printed onto a Bisaleimide triazine(BT) substrate with parallel transmission line(PTL) and coplanar waveguide(CPW) type, then was sintered at $250^{\circ}C$ for 30 min. We calculated the resistivity of printed circuits through direct current resistance by the measurement of I-V curve: the resistivity was approximately 0.558 ${\mu}{\Omega}{\cdot}cm$ which is about 3.3 times that of bulk Cu. Cascade's probe system in the frequency range from 0 to 30 GHz were employed to measure the Scattering parameter(S-parameter) with or without a gap between the substrate and the probe station chuck. The result of measured S-parameter showed that all printed circuits had over 5 dB of return loss in the entire frequency range. In the curve of insertion loss, $S_{21}$, showed that the PTL type circuits had better transmission of radio frequency (RF) than CPW type.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.19 no.6
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• pp.646-651
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• 2018

This paper reports that the electronic properties at a $P3HT/TiO_2$ interface associated with exciton dissociation and transport can be tailored by the insertion of a graphene quantum dot (GQD) layer. For donor/acceptor interface modification in an $ITO/TiO_2/P3HT/Al$ photovoltaic (PV) device, a continuous GQD film was prepared by a sonication treatment in solution that simplifies the conventional processes, including laser fragmentation and hydrothermal treatment, which limits a variety of component layers and involves low cost processing. The high conductivity and favorable energy alignment for exciton dissociation of the GQD layer increased the fill factor and short circuit current. The origin of the improved parameters is discussed in terms of the broad light absorption and enhanced interfacial carrier transport.

• Journal of IKEEE
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• v.24 no.3
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• pp.859-866
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• 2020

This paper proposes a 2-ch DC-DC converter with a wide-input voltage range from 2.9V~5.6V for wearable AMOLED displays. For positive voltage V_POS, a boost converter is designed using an over-charged voltage permissible circuit (OPC) which generates a normal output voltage even if over-input voltage is applied, and a SPWM-PWM dual mode with 3-segmented power transistors to improve efficiency at light load. For negative voltage V_NEG, a 0.5x regulated inverting charge pump is designed to increase power efficiency. The proposed DC-DC converter was designed using a 0.18-㎛ BCDMOS process. Simulation results show that the proposed DC-DC converter generates V_POS voltages of 4.6 V and V_NEG voltage of -0.6V~-2.3V for input voltage of 2.9V to 5.6V. In addition, it has power efficiency of 49%~92%, output ripple voltage has less than 20 mV for load current range of 1 mA~70 mA.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.20 no.12
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• pp.546-554
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• 2019

Typically, closed-circuit television (CCTV) monitoring is mainly used for post-processes (i.e. to provide evidence after an incident has occurred), but by using a streaming video feed, machine-based learning, and advanced image recognition techniques, current technology can be extended to respond to crimes or reports of missing persons in real time. The multi-CCTV cooperation technique developed in this study is a program model that delivers similarity information about a suspect (or moving object) extracted via CCTV at one location and sent to a monitoring agent to track the selected suspect or object when he, she, or it moves out of range to another CCTV camera. To improve the operating efficiency of local government CCTV control centers, we describe here the partial automation of a CCTV control system that currently relies upon monitoring by human agents. We envisage an integrated crime prevention service, which incorporates the cooperative CCTV network suggested in this study and that can easily be experienced by citizens in ways such as determining a precise individual location in real time and providing a crime prevention service linked to smartphones and/or crime prevention/safety information.

• Applied Chemistry for Engineering
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• v.24 no.1
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• pp.31-37
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• 2013

Lowering surface reflectance of Si wafers by texturization is one of the most important processes for improving the efficiency of Si solar cells. This paper presents the results on the effect of texturing using acidic solution mixtures containing the catalytic agents to moderate etching rates on the surface morphology of mc-Si wafer as well as on the performance parameters of solar cell. It was found that the treatment of contaminated crystalline silicon wafer with $HNO_3-H_2O_2-H_2O$ solution before the texturing helps the removal of organic contaminants due to its oxidizing properties and thereby allows the formation of nucleation centers for texturing. This treatment combined with the use of a catalytic agent such as phosphoric acid improved the effects of the texturing effects. This reduced the reflectance of the surface, thereby increased the short circuit current and the conversion efficiency of the solar cell. Employing this technique, we were able to fabricate mc-Si solar cell of 16.4% conversion efficiency with anti-reflective (AR) coating of silicon nitride film using plasma-enhanced chemical vapor deposition (PECVD) and Si wafers can be texturized in a short time.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2018.06a
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• pp.140-140
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• 2018

The 3D interconnect technologies have been appeared, as the density of Integrated Circuit (IC) devices increases. Through Silicon Via (TSV) process is an important technology in the 3D interconnect technologies. And the process is used to form a vertically electrical connection through silicon dies. This TSV process has some advantages that short length of interconnection, high interconnection density, low electrical resistance, and low power consumption. Because of these advantages, TSVs could improve the device performance higher. The fabrication process of TSV has several steps such as TSV etching, insulator deposition, seed layer deposition, metallization, planarization, and assembly. Among them, TSV metallization (i.e. TSV filling) was core process in the fabrication process of TSV because TSV metallization determines the performance and reliability of the TSV interconnect. TSVs were commonly filled with metals by using the simple electrochemical deposition method. However, since the aspect ratio of TSVs was become a higher, it was easy to occur voids and copper filling of TSVs became more difficult. Using some additives like an accelerator, suppressor and leveler for the void-free filling of TSVs, deposition rate of bottom could be fast whereas deposition of side walls could be inhibited. The suppressor was adsorbed surface of via easily because of its higher molecular weight than the accelerator. However, for high aspect ratio TSV fillers, the growth of the top of via can be accelerated because the suppressor is replaced by an accelerator. The substitution of the accelerator and the suppressor caused the side wall growth and defect generation. The suppressor was used as Single additive electrodeposition of TSV to overcome the constraints. At the electrochemical deposition of high aspect ratio of TSVs, the suppressor as single additive could effectively suppress the growth of the top surface and the void-free bottom-up filling became possible. Generally, copper was used to fill TSVs since its low resistivity could reduce the RC delay of the interconnection. However, because of the large Coefficients of Thermal Expansion (CTE) mismatch between silicon and copper, stress was induced to the silicon around the TSVs at the annealing process. The Keep Out Zone (KOZ), the stressed area in the silicon, could affect carrier mobility and could cause degradation of the device performance. Cobalt can be used as an alternative material because the CTE of cobalt was lower than that of copper. Therefore, using cobalt could reduce KOZ and improve device performance. In this study, high-aspect ratio TSVs were filled with cobalt using the electrochemical deposition. And the filling performance was enhanced by using the suppressor as single additive. Electrochemical analysis explains the effect of suppressor in the cobalt filling bath and the effect of filling behavior at condition such as current type was investigated.