• 제목/요약/키워드: Cu seed layer

검색결과 74건 처리시간 0.027초

Cu Seed Layer의 열처리에 따른 전해동도금 전착속도 개선 (Improvement of Electrodeposition Rate of Cu Layer by Heat Treatment of Electroless Cu Seed Layer)

  • 권병국;신동명;김형국;황윤회
    • 한국재료학회지
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    • 제24권4호
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    • pp.186-193
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    • 2014
  • A thin Cu seed layer for electroplating has been employed for decades in the miniaturization and integration of printed circuit board (PCB), however many problems are still caused by the thin Cu seed layer, e.g., open circuit faults in PCB, dimple defects, low conductivity, and etc. Here, we studied the effect of heat treatment of the thin Cu seed layer on the deposition rate of electroplated Cu. We investigated the heat-treatment effect on the crystallite size, morphology, electrical properties, and electrodeposition thickness by X-ray diffraction (XRD), atomic force microscope (AFM), four point probe (FPP), and scanning electron microscope (SEM) measurements, respectively. The results showed that post heat treatment of the thin Cu seed layer could improve surface roughness as well as electrical conductivity. Moreover, the deposition rate of electroplated Cu was improved about 148% by heat treatment of the Cu seed layer, indicating that the enhanced electrical conductivity and surface roughness accelerated the formation of Cu nuclei during electroplating. We also confirmed that the electrodeposition rate in the via filling process was also accelerated by heat-treating the Cu seed layer.

Cu seed layer 표면의 플라즈마 전처리가 Cu 전기도금 공정에 미치는 효과에 관한 연구 (Effects of Plasma Pretreatment of the Cu Seed Layer on Cu Electroplating)

  • 오준환;이성욱;이종무
    • 한국재료학회지
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    • 제11권9호
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    • pp.802-809
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    • 2001
  • Electroplating is an attractive alternative deposition method for copper with the need for a conformal and conductive seed layer In addition, the Cu seed layer should be highly pure so as not to compromise the effective resistivity of the filled copper interconnect structure. This seed layer requires low electrical resistivity, low levels of impurities, smooth interface, good adhesion to the barrier metal and low thickness concurrent with coherence for ensuring void-free fill. The electrical conductivity of the surface plays an important role in formation of initial Cu nuclei, Cu nucleation is much easier on the substrate with higher electrical conductivities. It is also known that the nucleation processes of Cu are very sensitive to surface condition. In this study, copper seed layers deposited by magnetron sputtering onto a tantalum nitride barrier layer were used for electroplating copper in the forward pulsed mode. Prior to electroplating a copper film, the Cu seed layer was cleaned by plasma H$_2$ and $N_2$. In the plasma treatment exposure tome was varied from 1 to 20 min and plasma power from 20 to 140W. Effects of plasma pretreatment to Cu seed/Tantalum nitride (TaN)/borophosphosilicate glass (BPSG) samples on electroplating of copper (Cu) films were investigated.

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전해도금을 위한 ALD Cu seed와 PVD Cu seed의 특성 비교

  • 김재경;박광민;한별;이원준;조성기;김재정
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.231-231
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    • 2010
  • 현재 Cu배선 제조공정에서 전해도금은 Damascene pattern의 Cu filling에 사용되고 있는데, 우수한 특성의 전해도금을 위해서는 step coverage가 우수한 Cu seed layer가 필수적이다. 현재까지 Cu seed layer를 형성하는 방법으로는 ionized physical vapor deposition(I-PVD)이 사용되고 있는데, 22 nm 이후의 소자에서는 step coverage의 한계로 인해 완벽한 Cu filling 어려울 것으로 예상된다. 본 연구에서는 step coverage가 매우 우수한 atomic layer deposition(ALD) 방법으로 Cu seed layer를 증착하고 그 특성을 기존의 PVD 박막과 비교하였다. Ketoiminate 계열의 +2가 Cu 전구체와 $H_2$를 이용하여 ALD Cu 박막을 증착하였는데 exposure, 기판의 온도를 변화시키면서 기판별로 ALD Cu의 최적공정조건을 도출하였다. ALD Cu seed와 PVD Cu seed 위에 약 $1{\mu}m$의 Cu 박막을 전해도금한 후 박막의 두께, 비저항, 미세구조와 함께 pattern filling 특성을 비교하였다.

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Formation of a MnSixOy barrier with Cu-Mn alloy film deposited using PEALD

  • Moon, Dae-Yong;Hwang, Chang-Mook;Park, Jong-Wan
    • 한국진공학회:학술대회논문집
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    • 한국진공학회 2009년도 제38회 동계학술대회 초록집
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    • pp.229-229
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    • 2010
  • With the scaling down of ultra large integrated circuits (ULSI) to the sub-50 nm technology node, the need for an ultra-thin, continuous and conformal diffusion barrier and Cu seed layer is increasing. However, diffusion barrier and Cu seed layer formation with a physical vapor deposition (PVD) method has become difficult as the technology node is reduced to 30 nm and beyond. Recent work on self-forming barrier processes using PVD Cu alloys have attracted great attention due to the capability of conformal ultra-thin barrier formation using a simple technique. However, as in the case of the conventional barrier and Cu seed layer, PVD of the Cu alloy seed layer will eventually encounter the difficulty in conformal deposition in narrow line trenches and via holes. Atomic layer deposition (ALD) has been known for its good step coverage and precise thickness control, and is a candidate technique for the formation of a thin conformal barrier layer and Cu seed layer. Conformal Cu-Mn seed layers were deposited by plasma enhanced atomic layer deposition (PEALD) at low temperature ($120^{\circ}C$), and the Mn content in the Cu-Mn alloys were controlled form 0 to approximately 10 atomic percent with various Mn precursor feeding times. Resistivity of the Cu-Mn alloy films decreased by annealing due to out-diffusion of Mn atoms. Out-diffused Mn atoms were segregated to the surface of the film and interface between a Cu-Mn alloy and $SiO_2$, resulting in self-formed $MnO_x$ and $MnSi_xO_y$, respectively. No inter-diffusion was observed between Cu and $SiO_2$ after annealing at $500^{\circ}C$ for 12 h, indicating an excellent diffusion barrier property of the $MnSi_xO_y$. The adhesion between Cu and $SiO_2$ was enhanced by the formation of $MnSi_xO_y$. Continuous and conductive Cu-Mn seed layers were deposited with PEALD into 32 nm $SiO_2$ trench, enabling a low temperature process, and the trench was perfectly filled using electrochemical plating (ECD) under conventional conditions. Thus, it is the resultant self-forming barrier process with PEALD Cu-Mn alloy film as a seed layer for plating Cu that has further potential to meet the requirement of the smaller than 30 nm node.

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약알칼리탈지 용액에서의 구리 Seed 층의 전처리 효과 (Effects of Pretreatment of Alkali-degreasing Solution for Cu Seed Layer)

  • 이연승;김성수;나사균
    • 한국진공학회지
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    • 제21권1호
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    • pp.6-11
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    • 2012
  • Sputter 방식으로 증착된 구리 seed 층(구리 seed/Ti/Si) 위에 형성된 오염물 제거과정을 이해하기 위하여, 강력한 계면 활성능력을 가진 약알칼리 탈지제 Metex TS-40A 용액을 사용하여 담금(dipping) 시간에 따른 구리 seed 층 표면의 변화형상 및 변화상태를 조사 분석하였다. Field emission scanning electron microscope을 이용하여 TS-40A 용액에 전처리 후 구리 seed 표면 형상이 grain이 명확히 보일 정도로 변화하는 것을 관찰하였고, X-ray photoelectron spectroscopy를 이용하여 표면 처리된 Cu seed 표면의 화학구조 및 불순물 상태를 조사하였다. TS-40 용액에서의 dipping 시간 변화에 따른 효과는 거의 없었다. TS-40A 용액에 전처리한 후, 구리 seed 층 표면위의 많은 탄소성분이 제거되었고, 약간의 산소가 제거되었으며, O=C 및 $Cu(OH)_2$에 해당되는 피크들이 감소되는 것이 관측되었다. 하지만 표면에서 불순물 Si이 silicate 상태로 검출되었다. TS-40A 용액에 포함되어 있는 silicate 성분이 구리 seed 층과 반응하여 이 silicate 불순물이 구리 seed 표면에 형성된 것으로 보여진다. 약알칼리 탈지제 Metex TS-40A 용액을 사용한 전처리 과정을 통해, 구리 seed 표면 위의 O=C 및 $Cu(OH)_2$ 등의 제거에는 탁월한 효과를 보였으나, 불순물 silicate가 형성되었으므로 이 알칼리 탈지제를 사용한다면, 이후에 산세정 및 다른 세정과정을 거쳐 표면에 존재하는 silicate를 제거할 필요성이 있다.

ENI 스퍼터를 이용한 Cu Seed Layer 증착

  • 이봉주;임선택;박영춘;유석재
    • 한국표면공학회:학술대회논문집
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    • 한국표면공학회 2008년도 추계학술대회 초록집
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    • pp.3-4
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    • 2008
  • 로직 디바이스에서는 알루미늄을 대신하여 구리로 backend-of-line(BEOL) 금속화공정이 대체되고 있다. 그러나 메모리 디바이스에서 구리 배선으로의 전환이 쉽지 않다. Cu-seed layer는 구리 배선을 메모리 디바이스에 적용하기 위해서 필요한 gap-fill 확장성을 개선하기 위한 중요한 부분을 차지한다. Cu-seed layer 증착을 위한 향상된 PVD 장비인 Eni 스퍼터를 소개한다.

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Self assembled-monolayer(SAM)법을 이용한 TaN 확산방지막의 무전해 Cu 도금용 Pd seed layer 제조 및 특성 (Pd Seed Layer for Electroless Cu Deposition on TaN Diffusion Barrier by Self-Assembled-Monolayer Method(SAM))

  • 한원규;조진기;최재웅;김정태;염승진;곽노정;김진웅;강성군
    • 한국재료학회지
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    • 제17권9호
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    • pp.469-474
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    • 2007
  • Electroless deposition(ELD) was applied to fabricate Cu interconnections on a TaN diffusion barrier with Pd seed layer. The Pd seed layer was obtained by self-assembled monolayer method(SAM) with PDDA and PSS as surfactants. We were able to obtain about 10nm Pd nano particles as seeds for electroless Cu deposition and the density of Pd seeds was much higher than that of Pd seeds fabricated by conventional Pd sensitization-activation method. Also we were able to obtain finer Cu interconnections by ELD. Therefore we concluded that the Pd seed layer by SAM was able to be applied to form Cu interconnection by ELD for under 30nm feature.

실리콘 실험실에 구리 오염을 방지 할 수 있는 고밀도/고균일의 Solder Bump 형성방법 (Fabrication Method of High-density and High-uniformity Solder Bump without Copper Cross-contamination in Si-LSI Laboratory)

  • 김성진;주철원;박성수;백규하;이희태;송민규
    • 마이크로전자및패키징학회지
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    • 제7권4호
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    • pp.23-29
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    • 2000
  • 사용되는 metal구분 없이 반도체 공정장비들을 사용함으로써 cross-contamination을 유발시킬 수 있다. 특히, copper(Cu)는 확산이 쉽게 되어 cross-contamination에 의해 수 ppm정도가 wafer에 오염되더라도 트랜지스터의 leakage current발생 요인으로 작용할 수 있기 때문에 Si-IC성능에 치명적인 영향을 미칠 수 있는데, Si-LSI 실험실에서 할 수 있는 공정과 Si-LSI 실험실을 나와 할 수 있는 공정으로 구분하여 최대한 Si-LSI 장비를 공유함으로써 최소한의 장비로 Cu cross-contamination문제를 해결할 수 있다. 즉, 전기도금을 할 때 전극으로 사용되어지는 TiW/Al sputtering, photoresist (PR) coating, solder bump형성을 위한 via형성까지는 Si-LSI 실험실에서 하고, 독립적인 다른 실험실에서 Cu-seed sputtering, solder 전기도금, 전극 etching, reflow공정을 하면 된다. 두꺼운 PR을 얻기 위하여 PR을 수회 도포(multiple coaling) 하고, 유기산 주석과 유기산 연의 비를 정확히 액 조성함으로서 Sn:Pb의 조성비가 6 : 4인 solder bump를 얻을 수 있었다. solder를 도금하기 전에 저속 도금으로 Cu를 도금하여, PR 표면의 Cu/Ti seed층을 via와 PR표면과의 저항 차를 이용하여 PR표면의 Cu-seed를 Cu도금 중에 etching 시킬 수 있다. 이러한 현상을 이용하여 선택적으로 via만 Cu를 도금하고 Ti층을 etching한 후, solder를 도금함으로써 저 비용으로 folder bump 높이가 60 $\mu\textrm{m}$ 이상 높고, 고 균일/고 밀도의 solder bump를 형성시킬 수 있었다.

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수소 환원기체와 (hfac)Cu(3,3-dimethyl-1-butene) 증착원을 이용한 Pulsed MOCVD로 Cu seed layer 증착 특성에 미치는 영향에 관한 연구 (Pulsed MOCVD of Cu Seed Layer Using a (hfac)Cu(3,3-dimethyl-1-butene) Source and H2 Reactant)

  • 박재범;이진형;이재갑
    • 한국재료학회지
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    • 제14권9호
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    • pp.619-626
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    • 2004
  • Pulsed metalorganic chemical vapor deposition (MOCVD) of conformal copper seed layers, for the electrodeposition Cu films, has been achieved by an alternating supply of a Cu(I) source and $H_2$ reactant at the deposition temperatures from 50 to $100^{\circ}C$. The Cu thickness increased proportionally to the number of cycles, and the growth rate was in the range from 3.5 to $8.2{\AA}/cycle$, showing the ability to control the nano-scale thickness. As-deposited films show highly smooth surfaces even for films thicker than 100 nm. In addition about a $90\%$ step coverage was obtained inside trenches, with an aspect ratio greater than 30:1. $H_2$, introduced as a reactant gas, can play an active role in achieving highly conformal coating, with increased grain sizes.

Copper Seed Layer 형성 및 도금 첨가제에 따른 Copper Via Filling (Formation of Copper Seed Layers and Copper Via Filling with Various Additives)

  • 이현주;지창욱;우성민;최만호;황윤회;이재호;김양도
    • 한국재료학회지
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    • 제22권7호
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    • pp.335-341
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    • 2012
  • Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.