• Korean Journal of Materials Research
• /
• v.24 no.4
• /
• pp.186-193
• /
• 2014

A thin Cu seed layer for electroplating has been employed for decades in the miniaturization and integration of printed circuit board (PCB), however many problems are still caused by the thin Cu seed layer, e.g., open circuit faults in PCB, dimple defects, low conductivity, and etc. Here, we studied the effect of heat treatment of the thin Cu seed layer on the deposition rate of electroplated Cu. We investigated the heat-treatment effect on the crystallite size, morphology, electrical properties, and electrodeposition thickness by X-ray diffraction (XRD), atomic force microscope (AFM), four point probe (FPP), and scanning electron microscope (SEM) measurements, respectively. The results showed that post heat treatment of the thin Cu seed layer could improve surface roughness as well as electrical conductivity. Moreover, the deposition rate of electroplated Cu was improved about 148% by heat treatment of the Cu seed layer, indicating that the enhanced electrical conductivity and surface roughness accelerated the formation of Cu nuclei during electroplating. We also confirmed that the electrodeposition rate in the via filling process was also accelerated by heat-treating the Cu seed layer.

• Korean Journal of Materials Research
• /
• v.11 no.9
• /
• pp.802-809
• /
• 2001

Electroplating is an attractive alternative deposition method for copper with the need for a conformal and conductive seed layer In addition, the Cu seed layer should be highly pure so as not to compromise the effective resistivity of the filled copper interconnect structure. This seed layer requires low electrical resistivity, low levels of impurities, smooth interface, good adhesion to the barrier metal and low thickness concurrent with coherence for ensuring void-free fill. The electrical conductivity of the surface plays an important role in formation of initial Cu nuclei, Cu nucleation is much easier on the substrate with higher electrical conductivities. It is also known that the nucleation processes of Cu are very sensitive to surface condition. In this study, copper seed layers deposited by magnetron sputtering onto a tantalum nitride barrier layer were used for electroplating copper in the forward pulsed mode. Prior to electroplating a copper film, the Cu seed layer was cleaned by plasma H$_2$ and $N_2$. In the plasma treatment exposure tome was varied from 1 to 20 min and plasma power from 20 to 140W. Effects of plasma pretreatment to Cu seed/Tantalum nitride (TaN)/borophosphosilicate glass (BPSG) samples on electroplating of copper (Cu) films were investigated.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.231-231
• /
• 2010

현재 Cu배선 제조공정에서 전해도금은 Damascene pattern의 Cu filling에 사용되고 있는데, 우수한 특성의 전해도금을 위해서는 step coverage가 우수한 Cu seed layer가 필수적이다. 현재까지 Cu seed layer를 형성하는 방법으로는 ionized physical vapor deposition(I-PVD)이 사용되고 있는데, 22 nm 이후의 소자에서는 step coverage의 한계로 인해 완벽한 Cu filling 어려울 것으로 예상된다. 본 연구에서는 step coverage가 매우 우수한 atomic layer deposition(ALD) 방법으로 Cu seed layer를 증착하고 그 특성을 기존의 PVD 박막과 비교하였다. Ketoiminate 계열의 +2가 Cu 전구체와 $H_2$를 이용하여 ALD Cu 박막을 증착하였는데 exposure, 기판의 온도를 변화시키면서 기판별로 ALD Cu의 최적공정조건을 도출하였다. ALD Cu seed와 PVD Cu seed 위에 약 $1{\mu}m$의 Cu 박막을 전해도금한 후 박막의 두께, 비저항, 미세구조와 함께 pattern filling 특성을 비교하였다.

• Proceedings of the Korean Vacuum Society Conference
• /
• 2010.02a
• /
• pp.229-229
• /
• 2010

With the scaling down of ultra large integrated circuits (ULSI) to the sub-50 nm technology node, the need for an ultra-thin, continuous and conformal diffusion barrier and Cu seed layer is increasing. However, diffusion barrier and Cu seed layer formation with a physical vapor deposition (PVD) method has become difficult as the technology node is reduced to 30 nm and beyond. Recent work on self-forming barrier processes using PVD Cu alloys have attracted great attention due to the capability of conformal ultra-thin barrier formation using a simple technique. However, as in the case of the conventional barrier and Cu seed layer, PVD of the Cu alloy seed layer will eventually encounter the difficulty in conformal deposition in narrow line trenches and via holes. Atomic layer deposition (ALD) has been known for its good step coverage and precise thickness control, and is a candidate technique for the formation of a thin conformal barrier layer and Cu seed layer. Conformal Cu-Mn seed layers were deposited by plasma enhanced atomic layer deposition (PEALD) at low temperature ($120^{\circ}C$), and the Mn content in the Cu-Mn alloys were controlled form 0 to approximately 10 atomic percent with various Mn precursor feeding times. Resistivity of the Cu-Mn alloy films decreased by annealing due to out-diffusion of Mn atoms. Out-diffused Mn atoms were segregated to the surface of the film and interface between a Cu-Mn alloy and $SiO_2$, resulting in self-formed $MnO_x$ and $MnSi_xO_y$, respectively. No inter-diffusion was observed between Cu and $SiO_2$ after annealing at $500^{\circ}C$ for 12 h, indicating an excellent diffusion barrier property of the $MnSi_xO_y$. The adhesion between Cu and $SiO_2$ was enhanced by the formation of $MnSi_xO_y$. Continuous and conductive Cu-Mn seed layers were deposited with PEALD into 32 nm $SiO_2$ trench, enabling a low temperature process, and the trench was perfectly filled using electrochemical plating (ECD) under conventional conditions. Thus, it is the resultant self-forming barrier process with PEALD Cu-Mn alloy film as a seed layer for plating Cu that has further potential to meet the requirement of the smaller than 30 nm node.

• Journal of the Korean Vacuum Society
• /
• v.21 no.1
• /
• pp.6-11
• /
• 2012

In order to understand a process of contaminants removal on surface of Cu seed layer (Cu seed/Ti/Si) by sputter deposition, we investigated the changed morphology and states of Cu seed surface after pretreatment in alkali degreasing Metex TS-40A solution according to dipping time. After TS-40A pretreatment, the surface morphology with clearer grains was observed by Field emission scanning electron microscope and the changed surface chemical states and impurities on surface of samples were checked by X-ray photoelectron spectroscopy. Dipping time in TS-40A solution had very little effect on surface of Cu seed layer. After pretreatment, much carbons and little oxygens on surface of Cu seed were eliminated and the decrease of peaks corresponded to O=C and $Cu(OH)_2$ was estimated. However, Si content (=silicate) was detected on sample surface. We think that the silicate impurity forms on Cu seed by chemical reaction of TS-40A solution included silicate component. By pretreatment of alkali degreasing Metex TS-40A solution, it showed an excellent effect in removal of O=C and $Cu(OH)_2$ on Cu seed layer, but the silicate was formed on surface of Cu seed. Therefore, another cleaning process such as acid cleaning is required for removal of this silicate in use of this alkali degreasing.

• Proceedings of the Korean Institute of Surface Engineering Conference
• /
• 2008.11a
• /
• pp.3-4
• /
• 2008

로직 디바이스에서는 알루미늄을 대신하여 구리로 backend-of-line(BEOL) 금속화공정이 대체되고 있다. 그러나 메모리 디바이스에서 구리 배선으로의 전환이 쉽지 않다. Cu-seed layer는 구리 배선을 메모리 디바이스에 적용하기 위해서 필요한 gap-fill 확장성을 개선하기 위한 중요한 부분을 차지한다. Cu-seed layer 증착을 위한 향상된 PVD 장비인 Eni 스퍼터를 소개한다.

• Korean Journal of Materials Research
• /
• v.17 no.9
• /
• pp.469-474
• /
• 2007

Electroless deposition(ELD) was applied to fabricate Cu interconnections on a TaN diffusion barrier with Pd seed layer. The Pd seed layer was obtained by self-assembled monolayer method(SAM) with PDDA and PSS as surfactants. We were able to obtain about 10nm Pd nano particles as seeds for electroless Cu deposition and the density of Pd seeds was much higher than that of Pd seeds fabricated by conventional Pd sensitization-activation method. Also we were able to obtain finer Cu interconnections by ELD. Therefore we concluded that the Pd seed layer by SAM was able to be applied to form Cu interconnection by ELD for under 30nm feature.

• Journal of the Microelectronics and Packaging Society
• /
• v.7 no.4
• /
• pp.23-29
• /
• 2000

We demonstrate the fabrication method of high-density and high-quality solder bump solving a copper (Cu) cross-contamination in Si-LSI laboratory. The Cu cross-contamination is solved by separating solder-bump process by two steps. Former is via-formation process excluding Cu/Ti under ball metallurgy (UBM) layer sputtering in Si-LSI laboratory. Latter is electroplating process including Ti-adhesion and Cu-seed layers sputtering out of Si-LSI laboratory. Thick photoresist (PR) is achieved by a multiple coating method. After TiW/Al-electrode sputtering for electroplating and via formation in Si-LSI laboratory, Cu/Ti UBM layer is sputtered on sample. The Cu-seed layer on the PR is etched during Cu-electroplating with low-electroplating rate due to a difference in resistance of UBM layer between via bottom and PR. Therefore Cu-buffer layer can be electroplated selectively at the via bottom. After etching the Ti-adhesion layer on the PR, Sn/Pb solder layer with a composition of 60/40 is electroplated using a tin-lead electroplating bath with a metal stoichiometry of 60/40 (weight percent ratio). Scanning electron microscope image shows that the fabricated solder bump is high-uniformity and high-quality as well as symmetric mushroom shape. The solder bumps with even 40/60 $\mu\textrm{m}$ in diameter/pitch do not touch during electroplating and reflow procedures. The solder-bump process of high-uniformity and high-density with the Cu cross-contamination free in Si-LSI laboratory will be effective for electronic microwave application.

• Korean Journal of Materials Research
• /
• v.14 no.9
• /
• pp.619-626
• /
• 2004

Pulsed metalorganic chemical vapor deposition (MOCVD) of conformal copper seed layers, for the electrodeposition Cu films, has been achieved by an alternating supply of a Cu(I) source and $H_2$ reactant at the deposition temperatures from 50 to $100^{\circ}C$. The Cu thickness increased proportionally to the number of cycles, and the growth rate was in the range from 3.5 to $8.2{\AA}/cycle$, showing the ability to control the nano-scale thickness. As-deposited films show highly smooth surfaces even for films thicker than 100 nm. In addition about a $90\%$ step coverage was obtained inside trenches, with an aspect ratio greater than 30:1. $H_2$, introduced as a reactant gas, can play an active role in achieving highly conformal coating, with increased grain sizes.

• Korean Journal of Materials Research
• /
• v.22 no.7
• /
• pp.335-341
• /
• 2012

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.