• Journal of the Microelectronics and Packaging Society
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• v.13 no.4
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• pp.57-63
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• 2006

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of electroplating current density and current mode. At $1.25mA/cm^{2}$ of DC mode, Cu filling ratio higher than 95% was obtained for trench vias of $75{\sim}35{\mu}m$ width. When electroplated at DC $2.5mA/cm^{2}$, Cu filling ratios became inferior to those processed at DC $1.25mA/cm^{2}$. Pulse current mode exhibited Cu filling characteristics superior to DC current mode.

• Journal of the Microelectronics and Packaging Society
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• v.14 no.3
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• pp.65-71
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• 2007

For chip-stack package applications, Cu filling characteristics into trench vias of $75{\sim}10\;{\mu}m$ width and 3 mm length were investigated with variations of the electroplating current density and the speed of a rotating disc electrode (RDE). Cu filling characteristics into trench vias were improved with increasing the RDE speed. There was a Nernst relationship between half width of trench vias of Cu filling ratio higher than 95% and the minimum RDE speed, and the half width of trenches with 95% Cu filling ratio was linearly proportional to the reciprocal of root of the minimum RED speed.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.117-123
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• 2014

Cu through-vias, which can be used as thermal vias or vertical interconnects, were formed using bottom-up electrodeposition filling as well as top-down electrodeposition filling into open via-holes and their microstructures were observed. Solid Cu through-vias without voids could be successfully formed by bottom-up filling as well as top-down filling with direct-current electrodeposition. While chemical-mechanical polishing (CMP) to remove the overplated Cu layer was needed on both top and bottom surfaces of the specimen processed by top-down filling method, the bottomup process has an advantage that such CMP was necessary only on the top surface of the sample.

• Proceedings of the Korean Institute of Surface Engineering Conference
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• 2016.11a
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• pp.128-128
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• 2016

Cu 배선폭 미세화 기술은 반도체 디바이스의 성능 향상을 위한 핵심 기술이다. 현재 배선 기술은 lithography, deposition, planarization등 종합적인 공정 기술의 발전에 따라 10x nm scale까지 감소하였다. 하지만 지속적인 feature size 감소를 위하여 요구되는 높은 공정 기술 및 비용과 배선폭 미세화로 인한 재료의 물리적 한계로 인하여 배선폭 미세화를 통한 성능의 향상에는 한계가 있다. 배선폭 미세화를 통한 2차원적인 집적도 향상과는 별개로 chip들의 3차원 적층을 통하여 반도체 디바이스의 성능 향상이 가능하다. 칩들의 3차원 적층을 위해서는 별도의 3차원 배선 기술이 요구되는데, TSV(through-Si-via)방식은 Si기판을 관통하는 via를 통하여 chip간의 전기신호 교환이 최단거리에서 이루어지는 가장 진보된 형태의 3차원 배선 기술이다. Si 기판에 $50{\mu}m$이상 깊이의 via 및 seed layer를 형성 한 후 습식전해증착법을 이용하여 Cu 배선이 이루어지는데, via 내부 Cu ion 공급 한계로 인하여 일반적인 공정으로는 void와 같은 defect가 형성되어 배선 신뢰성에 문제를 발생시킨다. 이를 해결하기 위해 각종 유기 첨가제가 사용되는데, suppressor를 사용하여 Si 기판 상층부와 via 측면벽의 Cu 증착을 억제하고, accelerator를 사용하여 via 바닥면의 Cu 성장속도를 증가시켜 bottom-up TSV filling을 유도하는 방식이 일반적이다. 이론적으로, Bottom-up TSV filling은 sample 전체에서 Cu 성장을 억제하는 suppressor가 via bottom의 강한 potential로 인하여 국부적 탈착되고 via bottom에서만 Cu가 증착되어 되어 이루어지므로, accelerator가 없이도 void-free TSV filling이 가능하다. Accelerator가 Suppressor를 치환하여 오히려 bottom-up TSV filling을 방해한다는 보고도 있었다. 본 연구에서는 유기 첨가제의 치환으로 인한 TSV filling performance 저하를 방지하고, 유기 첨가제 조성을 단순화하여 용액 관리가 용이하도록 하기 위하여 suppressor만을 이용한 TSV filling 연구를 진행하였다. 먼저, suppressor의 흡착, 탈착 특성을 이해하기 위한 연구가 진행되었고, 이를 바탕으로 suppressor만을 이용한 bottom-up Cu TSV filling이 진행되었다. 최종적으로 $60{\mu}m$ 깊이의 TSV를 1000초 내에 void-free filling하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.231-231
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• 2010

현재 Cu배선 제조공정에서 전해도금은 Damascene pattern의 Cu filling에 사용되고 있는데, 우수한 특성의 전해도금을 위해서는 step coverage가 우수한 Cu seed layer가 필수적이다. 현재까지 Cu seed layer를 형성하는 방법으로는 ionized physical vapor deposition(I-PVD)이 사용되고 있는데, 22 nm 이후의 소자에서는 step coverage의 한계로 인해 완벽한 Cu filling 어려울 것으로 예상된다. 본 연구에서는 step coverage가 매우 우수한 atomic layer deposition(ALD) 방법으로 Cu seed layer를 증착하고 그 특성을 기존의 PVD 박막과 비교하였다. Ketoiminate 계열의 +2가 Cu 전구체와 $H_2$를 이용하여 ALD Cu 박막을 증착하였는데 exposure, 기판의 온도를 변화시키면서 기판별로 ALD Cu의 최적공정조건을 도출하였다. ALD Cu seed와 PVD Cu seed 위에 약 $1{\mu}m$의 Cu 박막을 전해도금한 후 박막의 두께, 비저항, 미세구조와 함께 pattern filling 특성을 비교하였다.

• Proceedings of the Korean Vacuum Society Conference
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• 2012.02a
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• pp.370-370
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• 2012

Feature size of Cu interconnects keep shrinking into several tens of nanometer level. For this reason, the Cu interconnects face challenging issues such as increase of electro-migration, line-width dependent electrical resistivity increase, and gap-filling difficulty in high aspect ratio structures. As the thickness of the Cu film decreases below 30 nm, the electrical resistivity is not any more constant, but rather exponential. Research on alloying with other elements have been started to inhibit such escalation in the electrical resistivity. A faint trace of Al added in Cu film by sputtering was reported to contribute to suppression of the increase of the electrical resistivity. From an industrial point of view, we introduced cyclic metal organic chemical vapor deposition (MOCVD) in order to control Al concentration in the Cu film more easily by controlling the delivery time ratio of Cu and Al precursors. The amount of alloying element could be lowered at level of below 1 at%. Process of the alloy formation was applied into gap-filling to evaluate the performance of the gap-filling. Voidless gap-filling even into high aspect ratio trenches was achieved. In-depth analysis will be discussed in detail.

• Journal of the Microelectronics and Packaging Society
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• v.21 no.4
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• pp.91-96
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• 2014

Through silicon via (TSV) technology is to form a via hole in a silicon chip, and to stack the chips vertically for three-dimensional (3D) electronics packaging technology. This can reduce current path, power consumption and response time. In this study, Cu-filling substrate size was changed from Si-chip to a 4" wafer to investigate the behavior of Cu filling in wafer level. The electrolyte for Cu filling consisted of $CuSO_4$ $5H_2O$, $H_2SO_4$ and small amount of additives. The anode was Pt, and cathode was changed from $0.5{\times}0.5cm^2$ to 4" wafer. As experimental results, in the case of $5{\times}5cm^2$ Si chip, suitable distance of electrodes was 4cm having 100% filling ratio. The distance of 0~0.5 cm from current supplying location showed 100% filling ratio, and distance of 4.5~5 cm showed 95%. It was confirmed good TSV filling was achieved by plating for 2.5 hrs.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.08a
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• pp.246-246
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• 2010

As the trench width in the interconnect technology decreases down to nano-scale below 50 nm, superconformal gap-filling process of Cu becomes very critical for Cu interconnect. Obtaining superconfomral gap-filling of Cu in the nano-scale trench or via hole using MOCVD is essential to control nucleation and growth of Cu. Therefore, nucleation of Cu must be suppressed near the entrance surface of the trench while Cu layer nucleates and grows at the bottom of the trench. In this study, suppression of Cu nucleation was achieved by treating the Ru barrier metal surface with capacitively coupled hydrogen plasma. Effect of hydrogen plasma pretreatment on Cu nucleation was investigated during MOCVD on atomic-layer deposited (ALD)-Ru barrier surface. It was found that the nucleation and growth of Cu was affected by hydrogen plasma treatment condition. In particular, as the plasma pretreatment time and electrode power increased, Cu nucleation was inhibited. Experimental data suggests that hydrogen atoms from the plasma was implanted onto the Ru surface, which resulted in suppression of Cu nucleation owing to prevention of adsorption of Cu precursor molecules. Due to the hydrogen plasma treatment of the trench on Ru barrier surface, the suppression of Cu nucleation near the entrance of the trenches was achieved and then led to the superconformal gap filling of the nano-scale trenches. In the case for without hydrogen plasma treatments, however, over-grown Cu covered the whole entrance of nano-scale trenches. Detailed mechanism of nucleation suppression and resulting in nano-scale superconformal gap-filling of Cu will be discussed in detail.

• Korean Journal of Materials Research
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• v.22 no.7
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• pp.335-341
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• 2012

Recently, the demand for the miniaturization of printed circuit boards has been increasing, as electronic devices have been sharply downsized. Conventional multi-layered PCBs are limited in terms their use with higher packaging densities. Therefore, a build-up process has been adopted as a new multi-layered PCB manufacturing process. In this process, via-holes are used to connect each conductive layer. After the connection of the interlayers created by electro copper plating, the via-holes are filled with a conductive paste. In this study, a desmear treatment, electroless plating and electroplating were carried out to investigate the optimum processing conditions for Cu via filling on a PCB. The desmear treatment involved swelling, etching, reduction, and an acid dip. A seed layer was formed on the via surface by electroless Cu plating. For Cu via filling, the electroplating of Cu from an acid sulfate bath containing typical additives such as PEG(polyethylene glycol), chloride ions, bis-(3-sodiumsulfopropyl disulfide) (SPS), and Janus Green B(JGB) was carried out. The desmear treatment clearly removes laser drilling residue and improves the surface roughness, which is necessary to ensure good adhesion of the Cu. A homogeneous and thick Cu seed layer was deposited on the samples after the desmear treatment. The 2,2'-Dipyridyl additive significantly improves the seed layer quality. SPS, PEG, and JGB additives are necessary to ensure defect-free bottom-up super filling.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.249-249
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• 2010

The effect of forming a passivation layer was investigated in superconformal Cu gap-filling of the nano-scale trench with atomic-layer deposited (ALD)-Ru glue layer. It was discovered that the nucleation and growth of Cu during metal-organic chemical vapor deposition (MOCVD) were affected by hydrogen plasma treatments. Specifically, as the plasma pretreatment time increased, Cu nucleation was suppressed proportionally. XPS and Thermal Desorption Spectroscopy indicated that hydrogen atoms passivate the Ru surface, which leads to suppression of Cu nucleation owing to prevention of adsorption of Cu precursor molecules. For gap-fill property, sub 60-nm ALD Ru trenches without the plasma pretreatment was blocked by overgrown Cu after the Cu deposition. With the plasma pretreatment, superconformal gap filling of the nano-scale trenches was achieved due to the suppression of Cu nucleation near the entrances of the trenches. Even the plasma pretreatment with bottom bias leads to the superconformal gap-filling.